Unformatted text preview: the third element of the second operand. HADDPD Performs a doubleprecision addition on contiguous data elements. The first data element of the result is obtained by adding the first and second elements of the first operand; the second element by adding the first and second elements of the second operand. Performs a doubleprecision subtraction on contiguous data elements. The first data element of the result is obtained by subtracting the second element of the first operand from the first element of the first operand; the second element by subtracting the second element of the second operand from the first element of the second operand. HSUBPD 5.7.5
MOVSHDUP MOVSLDUP MOVDDUP SSE3 SIMD FloatingPoint LOAD/MOVE/DUPLICATE Instructions
Loads/moves 128 bits; duplicating the second and fourth 32bit data elements Loads/moves 128 bits; duplicating the first and third 32bit data elements Loads/moves 64 bits (bits[63:0] if the source is a register) and returns the same 64 bits in both the lower and upper halves of the 128bit result register; duplicates the 64 bits from the source 5.7.6
MONITOR MWAIT SSE3 Agent Synchronization Instructions
Sets up an address range used to monitor writeback stores Enables a logical processor to enter into an optimized state while waiting for a writeback store to the address range set up by the MONITOR instruction Vol. 1 527 INSTRUCTION SET SUMMARY 5.8 SUPPLEMENTAL STREAMING SIMD EXTENSIONS 3 (SSSE3) INSTRUCTIONS SSSE3 provide 32 instructions (represented by 14 mnemonics) to accelerate computations on packed integers. These include: Twelve instructions that perform horizontal addition or subtraction operations. Six instructions that evaluate absolute values. Two instructions that perform multiply and add operations and speed up the evaluation of dot products. Two instructions that accelerate packedinteger multiply operations and produce integer values with scaling. Two instructions that perform a bytewise, inplace shuffle according to the second shuffle control operand. Six instructions that negate packed integers in the destination operand if the signs of the corresponding element in the source operand is less than zero. Two instructions that align data from the composite of two operands. SSSE3 instructions can only be executed on Intel 64 and IA32 processors that support SSSE3 extensions. Support for these instructions can be detected with the CPUID instruction. See the description of the CPUID instruction in Chapter 3, "Instruction Set Reference, AM," of the Intel 64 and IA32 Architectures Software Developer's Manual, Volume 2A. The sections that follow describe each subgroup. 5.8.1
PHADDW Horizontal Addition/Subtraction
Adds two adjacent, signed 16bit integers horizontally from the source and destination operands and packs the signed 16bit results to the destination operand. Adds two adjacent, signed 16bit integers horizontally from the source and destination operands and packs the signed, satura...
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 Winter '11
 Watlins
 X86, Intel corporation, 64bit mode, fpu floatingpoint exception, FPU Control Instructions

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