Unformatted text preview: s a biased exponent greater than the largest allowable exponent for the selected result format. 22.214.171.124 NaNs Since NaNs are non-numbers, they are not part of the real number line. In Figure 4-12, the encoding space for NaNs in the floating-point formats is shown Vol. 1 4-19 DATA TYPES above the ends of the real number line. This space includes any value with the maximum allowable biased exponent and a non-zero fraction (the sign bit is ignored for NaNs). The IA-32 architecture defines two classes of NaNs: quiet NaNs (QNaNs) and signaling NaNs (SNaNs). A QNaN is a NaN with the most significant fraction bit set; an SNaN is a NaN with the most significant fraction bit clear. QNaNs are allowed to propagate through most arithmetic operations without signaling an exception. SNaNs generally signal a floating-point invalid-operation exception whenever they appear as operands in arithmetic operations. SNaNs are typically used to trap or invoke an exception handler. They must be inserted by software; that is, the processor never generates an SNaN as a result of a floating-point operation. 126.96.36.199 Operating on SNaNs and QNaNs When a floating-point operation is performed on an SNaN and/or a QNaN, the result of the operation is either a QNaN delivered to the destination operand or the generation of a floating-point invalid operating exception, depending on the following rules: If one of the source operands is an SNaN and the floating-point invalid-operating exception is not masked (see Section 188.8.131.52, "Invalid Operation Exception (#I)"), the a floating-point invalid-operation exception is signaled and no result is stored in the destination operand. If either or both of the source operands are NaNs and floating-point invalidoperation exception is masked, the result is as shown in Table 4-7. When an SNaN is converted to a QNaN, the conversion is handled by setting the mostsignificant fraction bit of the SNaN to 1. Also, when one of the source operands is an SNaN, the floating-point invalid-operation exception flag it set. Note that for some combinations of source operands, the result is different for x87 FPU operations and for SSE/SSE2/SSE3 operations. When neither of the source operands is a NaN, but the operation generates a floating-point invalid-operation exception (see Tables 8-10 and 11-1), the result is commonly an SNaN source operand converted to a QNaN or the QNaN floatingpoint indefinite value. Any exceptions to the behavior described in Table 4-7 are described in Section 184.108.40.206, "Invalid Arithmetic Operand Exception (#IA)," and Section 220.127.116.11, "Invalid Operation Exception (#I)." 4-20 Vol. 1 DATA TYPES Table 4-7. Rules for Handling NaNs
Source Operands SNaN and QNaN Result1 x87 FPU -- QNaN source operand. SSE/SSE2/SSE3 -- First operand (if this operand is an SNaN, it is converted to a QNaN) Two SNaNs x87 FPU--SNaN source operand with the larger significand, converted into a QNaN SSE/SSE2/SSE3 -- First operand converted...
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- Winter '11
- X86, Intel corporation, 64-bit mode, fpu floating-point exception, FPU Control Instructions