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Unformatted text preview: ypes, 10-8, 12-1 denormal operand exception (#D), 11-21 denormals-are-zeros mode, 10-7 divide by zero exception (#Z), 11-22 exceptions, 11-18 floating-point format, 4-13, 4-14 flush-to-zero mode, 10-7 generating SIMD FP exceptions, 11-23 guidelines for using, 11-27 handling combinations of masked and unmasked exceptions, 11-26 handling masked exceptions, 11-23 handling SIMD floating-point exceptions in software, 11-26 handling unmasked exceptions, 11-25, 11-26 inexact result exception (#P), 11-23 instruction prefixes, effect on SSE and SSE2 instructions, 11-37 instruction set, 5-16, 10-9 interaction of SIMD and x87 FPU floating-point exceptions, 11-26 interaction of SSE and SSE2 instructions with x87 FPU and MMX instructions, 11-31 interfacing with SSE and SSE2 procedures and functions, 11-34 intermixing packed and scalar floating-point and 128-bit SIMD integer instructions and data, 11-32 introduction, 2-4 invalid operation exception (#I), 11-20 logical instructions, 10-13 masked responses to invalid arithmetic operations, 11-20 memory ordering instruction, 10-20 MMX technology compatibility, 10-8 MXCSR register, 10-5 MXCSR state management instructions, 10-17 non-temporal data, operating on, 10-18 numeric overflow exception (#O), 11-22 numeric underflow exception (#U), 11-22 overview, 10-1 packed 128-Bit SIMD data types, 4-11 packed and scalar floating-point instructions, 10-9 programming environment, 10-3 QNaN floating-point indefinite, 4-22 restoring SSE and SSE2 state, 11-30 REX prefixes, 10-4 saving SSE and SSE2 state, 11-30 saving XMM register state on a procedure or function call, 11-34 shuffle instructions, 10-14 SIMD floating-point exception conditions, 11-19 SIMD floating-point exception cross reference, C-4 SIMD floating-point exception (#XF), 11-25, 11-26 SIMD floating-point exceptions, 11-19 SIMD floating-point mask and flag bits, 10-6 SIMD floating-point rounding control field, 10-6 SSE and SSE2 conversion instruction chart, 11-13 SSE feature flag, CPUID instruction, 11-28 SSE2 compatibility, 10-8 unpack instructions, 10-14 updating MMX technology routines using128-bit SIMD integer instructions, 11-35 x87 FPU compatibility, 10-8 XMM registers, 10-4 SSE feature flag, CPUID instruction, 11-28, 12-7 SSE instructions descriptions of, 10-9 SIMD floating-point exception cross-reference, C-4 summary of, 5-16 SSE2 extensions 128-bit packed single-precision data type, 11-4 128-bit packed single-precision data type, 12-2 128-bit SIMD integer instruction extensions, 11-16 64-bit and 128-bit SIMD integer instructions, 11-15 64-bit mode, 11-4 arithmetic instructions, 11-8 branch hints, 11-18 branching on arithmetic operations, 11-36 cacheability control instructions, 11-17 cacheability hint instructions, 11-36 caller-save requirement for procedure and function calls, 11-35 checking for SSE and SSE2 support, 11-28 comparison instructions, 11-10 compatibility mode, 11-4 compatibility of SIMD and x87 FPU floating-point data types, 11-32 conversion...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.
- Winter '11