Unformatted text preview: tack into the EIP register. Program execution then continues with the instruction pointed to by the EIP register. The RET instruction has an optional operand, the value of which is added to the contents of the ESP register as part of the return operation. This operand allows the stack pointer to be incremented to remove parameters from the stack that were pushed on the stack by the calling procedure. See Section 6.3, "Calling Procedures Using CALL and RET," for more information on the mechanics of making procedure calls with the CALL and RET instructions. Return from interrupt instruction -- When the processor services an interrupt, it performs an implicit call to an interrupt-handling procedure. The IRET (return from interrupt) instruction returns program control from an interrupt handler to the interrupted procedure (that is, the procedure that was executing when the interrupt occurred). The IRET instruction performs a similar operation to the RET instruction (see "Call and return instructions" on page 7-21) except that it also restores the EFLAGS register from the stack. The contents of the EFLAGS register are automatically stored on the stack along with the return instruction pointer when the processor services an interrupt. Vol. 1 7-21 PROGRAMMING WITH GENERAL-PURPOSE INSTRUCTIONS 220.127.116.11 Conditional Transfer Instructions The conditional transfer instructions execute jumps or loops that transfer program control to another instruction in the instruction stream if specified conditions are met. The conditions for control transfer are specified with a set of condition codes that define various states of the status flags (CF, ZF, OF, PF, and SF) in the EFLAGS register. Conditional jump instructions -- The Jcc (conditional) jump instructions transfer program control to a destination instruction if the conditions specified with the condition code (cc) associated with the instruction are satisfied (see Table 7-4). If the condition is not satisfied, execution continues with the instruction following the Jcc instruction. As with the JMP instruction, the transfer is one-way; that is, a return address is not saved. Table 7-4. Conditional Jump Instructions
Instruction Mnemonic Unsigned Conditional Jumps JA/JNBE JAE/JNB JB/JNAE JBE/JNA JC JE/JZ JNC JNE/JNZ JNP/JPO JP/JPE JCXZ JECXZ Signed Conditional Jumps JG/JNLE JGE/JNL JL/JNGE JLE/JNG JNO JNS JO JS ((SF xor OF) or ZF) = 0 (SF xor OF) = 0 (SF xor OF) = 1 ((SF xor OF) or ZF) = 1 OF = 0 SF = 0 OF = 1 SF = 1 Greater/not less or equal Greater or equal/not less Less/not greater or equal Less or equal/not greater Not overflow Not sign (non-negative) Overflow Sign (negative) (CF or ZF) = 0 CF = 0 CF = 1 (CF or ZF) = 1 CF = 1 ZF = 1 CF = 0 ZF = 0 PF = 0 PF = 1 CX = 0 ECX = 0 Above/not below or equal Above or equal/not below Below/not above or equal Below or equal/not above Carry Equal/zero Not carry Not equal/not zero Not parity/parity odd Parity/parity even Register CX is zero Register ECX is zero...
View Full Document
- Winter '11
- X86, Intel corporation, 64-bit mode, fpu floating-point exception, FPU Control Instructions