ia-32_volume1_basic-arch

Elements of signed words doublewords are supported

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Unformatted text preview: tem supports SSE/SSE2/SSE3/SSSE3 extensions. (Operating system support for the SSE extensions implies support for SSE2, the x87, SIMD instructions of SSE3, and SSSE3.) Employ the optimization and scheduling techniques described in the Intel 64 and IA-32 Architectures Optimization Reference Manual (see Section 1.4, "Related Literature"). Vol. 1 12-13 PROGRAMMING WITH SSE3 AND SUPPLEMENTAL SSE3 12.7.2 Checking for SSSE3 Support Before an application attempts to use the SIMD subset of SSSE3 extensions, the application should follow the steps illustrated in Section 11.6.2, "Checking for SSE/SSE2 Support." Next, use the additional step provided below: Check that the processor supports the SIMD and x87 SSSE3 extensions (if CPUID.01H:ECX.SSSE3[bit 9] = 1). See Example 12-3 for a code example. Example 12-3. Verifying SSSE3 Support boolean SSSE3_SIMD_works = TRUE; try { Issue_SSSE3_SIMD_Instructions(); // Use PHADDD } except (UNWIND) { // if we get here, SSSE3 not available SSSE3_SIMD_works = FALSE; } 12.8 SSE3/SSSE3 EXCEPTIONS SSE3/SSSE3 instructions can generate the same type of memory-access and nonnumeric exceptions as other Intel 64 or IA-32 instructions. Existing exception handlers generally handle these exceptions without code modification. FISTTP can generate floating-point exceptions. Some SSE3 instructions can also generate SIMD floating-point exceptions. SSE3 additions and changes are noted in the following sections. See also: Section 11.5, "SSE, SSE2, and SSE3 Exceptions" 12.8.1 Device Not Available (DNA) Exceptions SSE3/SSSE3 will cause a DNA Exception (#NM) if the processor attempts to execute an SSE3 instruction while CR0.TS[bit 3] = 1. If CPUID.01H:ECX.SSE3[bit 0] = 0, execution of an SSE3 extension will cause an invalid opcode fault regardless of the state of CR0.TS[bit 3]. 12-14 Vol. 1 PROGRAMMING WITH SSE3 AND SUPPLEMENTAL SSE3 12.8.2 Numeric Error flag and IGNNE# Most SSE3 instructions ignore CR0.NE[bit 5] (treats it as if it were always set) and the IGNNE# pin. With one exception, all use the vector 19 software exception for error reporting. The exception is FISTTP; it behaves like other x87-FP instructions. SSSE3 instructions ignore CR0.NE[bit 5] (treats it as if it were always set) and the IGNNE# pin. SSSE3 instructions do not cause floating-point errors. 12.8.3 Emulation Used to emulate x87 floating-point instructions, CR0.EM[bit 2] cannot be used for emulation of SSE3/SSSE3. If an SSE3/SSSE3 instruction executes with CR0.EM[bit 2] set, an invalid opcode exception (INT 6) is generated instead of a device not available exception (INT 7). Vol. 1 12-15 PROGRAMMING WITH SSE3 AND SUPPLEMENTAL SSE3 12-16 Vol. 1 CHAPTER 13 INPUT/OUTPUT In addition to transferring data to and from external memory, IA-32 processors can also transfer data to and from input/output ports (I/O ports). I/O ports are created in system hardware by circuity that decodes the control, data, and address pins on the processor. These I/O ports...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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