Unformatted text preview: east significant bit of the operand. When the processor identifies the bit to be tested and modified, it first loads the CF flag with the current value of the bit. Then it assigns a new value to the selected bit, as determined by the modify operation for the instruction. Table 7-3. Bit Test and Modify Instructions
Instruction BT (Bit Test) BTS (Bit Test and Set) BTR (Bit Test and Reset) BTC (Bit Test and Complement) Effect on CF Flag CF flag Selected Bit CF flag Selected Bit CF flag Selected Bit CF flag Selected Bit Effect on Selected Bit No effect Selected Bit 1 Selected Bit 0 Selected Bit NOT (Selected Bit) 18.104.22.168 Bit Scan Instructions The BSF (bit scan forward) and BSR (bit scan reverse) instructions scan a bit string in a source operand for a set bit and store the bit index of the first set bit found in a destination register. The bit index is the offset from the least significant bit (bit 0) in the bit string to the first set bit. The BSF instruction scans the source operand low-tohigh (from bit 0 of the source operand toward the most significant bit); the BSR instruction scans high-to-low (from the most significant bit toward the least significant bit). 22.214.171.124 Byte Set on Condition Instructions The SETcc (set byte on condition) instructions set a destination-operand byte to 0 or 1, depending on the state of selected status flags (CF, OF, SF, ZF, and PF) in the EFLAGS register. The suffix (cc) added to the SET mnemonic determines the condition being tested for. For example, the SETO instruction tests for overflow. If the OF flag is set, the destination byte is set to 1; if OF is clear, the destination byte is cleared to 0. Appendix B, Vol. 1 7-19 PROGRAMMING WITH GENERAL-PURPOSE INSTRUCTIONS "EFLAGS Condition Codes," lists the conditions it is possible to test for with this instruction. 126.96.36.199 Test Instruction The TEST instruction performs a logical AND of two operands and sets the SF, ZF, and PF flags according to the results. The flags can then be tested by the conditional jump or loop instructions or the SETcc instructions. The TEST instruction differs from the AND instruction in that it does not alter either of the operands. 7.3.8 Control Transfer Instructions The processor provides both conditional and unconditional control transfer instructions to direct the flow of program execution. Conditional transfers are taken only for specified states of the status flags in the EFLAGS register. Unconditional control transfers are always executed. For the purpose of this discussion, these instructions are further divided subordinate subgroups that process: Unconditional transfers Conditional transfers Software interrupts 188.8.131.52 Unconditional Transfer Instructions The JMP, CALL, RET, INT, and IRET instructions transfer program control to another location (destination address) in the instruction stream. The destination can be within the same code segment (near transfer) or in a different code segment (far transfer). Jump instruction -- The...
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- Winter '11
- X86, Intel corporation, 64-bit mode, fpu floating-point exception, FPU Control Instructions