Unformatted text preview: l zeros). Vol. 1 11-29 PROGRAMMING WITH STREAMING SIMD EXTENSIONS 2 (SSE2) Table 11-2. SSE and SSE2 State Following a Power-up/Reset or INIT
Registers XMM0 through XMM7 MXCSR Power-Up or Reset +0.0 1F80H Unchanged Unchanged INIT If the processor is reset by asserting the INIT# pin, the SSE and SSE2 state is not changed. 11.6.5 Saving and Restoring the SSE/SSE2 State The FXSAVE instruction saves the x87 FPU, MMX, SSE and SSE2 states (which includes the contents of eight XMM registers and the MXCSR registers) in a 512-byte block of memory. The FXRSTOR instruction restores the saved SSE and SSE2 state from memory. See the FXSAVE instruction in Chapter 3 of the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2A, for the layout of the 512-byte state block. In addition to saving and restoring the SSE and SSE2 state, FXSAVE and FXRSTOR also save and restore the x87 FPU state (because MMX registers are aliased to the x87 FPU data registers this includes saving and restoring the MMX state). For greater code efficiency, it is suggested that FXSAVE and FXRSTOR be substituted for the FSAVE, FNSAVE and FRSTOR instructions in the following situations: When a context switch is being made in a multitasking environment During calls and returns from interrupt and exception handlers In situations where the code is switching between x87 FPU and MMX technology computations (without a context switch or a call to an interrupt or exception), the FSAVE/FNSAVE and FRSTOR instructions are more efficient than the FXSAVE and FXRSTOR instructions. 11.6.6 Guidelines for Writing to the MXCSR Register The MXCSR has several reserved bits, and attempting to write a 1 to any of these bits will cause a general-protection exception (#GP) to be generated. To allow software to identify these reserved bits, the MXCSR_MASK value is provided. Software can determine this mask value as follows: 1. Establish a 512-byte FXSAVE area in memory. 2. Clear the FXSAVE area to all 0s. 3. Execute the FXSAVE instruction, using the address of the first byte of the cleared FXSAVE area as a source operand. See "FXSAVE--Save x87 FPU, MMX, SSE, and SSE2 State" in Chapter 3 of the Intel 64 and IA-32 Architectures Software 11-30 Vol. 1 PROGRAMMING WITH STREAMING SIMD EXTENSIONS 2 (SSE2) Developer's Manual, Volume 2A, for a description of FXSAVE and the layout of the FXSAVE image. 4. Check the value in the MXCSR_MASK field in the FXSAVE image (bytes 28 through 31). -- If the value of the MXCSR_MASK field is 00000000H, then the MXCSR_MASK value is the default value of 0000FFBFH. Note that this value indicates that bit 6 of the MXCSR register is reserved; this setting indicates that the denormals-are-zero mode is not supported on the processor. -- If the value of the MXCSR_MASK field is non-zero, the MXCSR_MASK value should be used as the MXCSR_MASK. All bits set to 0 in the MXCSR_MASK value indicate reserved bits in the MXCSR register. Thus, if the MXCSR_MASK value is AND'd with a v...
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- Winter '11
- X86, Intel corporation, 64-bit mode, fpu floating-point exception, FPU Control Instructions