Unformatted text preview: e In compatibility mode and 64-bit mode, MMX instructions function like they do in protected mode. Memory operands are specified using the ModR/M, SIB encoding described in Section 3.7.5. 9-2 Vol. 1 PROGRAMMING WITH INTEL MMXTM TECHNOLOGY 9.2.2 MMX Registers The MMX register set consists of eight 64-bit registers (see Figure 9-2), that are used to perform calculations on the MMX packed integer data types. Values in MMX registers have the same format as a 64-bit quantity in memory. The MMX registers have two data access modes: 64-bit access mode and 32-bit access mode. The 64-bit access mode is used for: 64-bit memory accesses 64-bit transfers between MMX registers All pack, logical, and arithmetic instructions Some unpack instructions 32-bit memory accesses 32-bit transfer between general-purpose registers and MMX registers Some unpack instructions
63 MM7 MM6 MM5 MM4 MM3 MM2 MM1 MM0 0 The 32-bit access mode is used for: Figure 9-2. MMX Register Set
Although MMX registers are defined in the IA-32 architecture as separate registers, they are aliased to the registers in the FPU data register stack (R0 through R7). See also Section 9.5, "Compatibility with x87 FPU Architecture." Vol. 1 9-3 PROGRAMMING WITH INTEL MMXTM TECHNOLOGY 9.2.3 MMX Data Types MMX technology introduced the following 64-bit data types to the IA-32 architecture (see Figure 9-3): 64-bit packed byte integers -- eight packed bytes 64-bit packed word integers -- four packed words 64-bit packed doubleword integers -- two packed doublewords MMX instructions move 64-bit packed data types (packed bytes, packed words, or packed doublewords) and the quadword data type between MMX registers and memory or between MMX registers in 64-bit blocks. However, when performing arithmetic or logical operations on the packed data types, MMX instructions operate in parallel on the individual bytes, words, or doublewords contained in MMX registers (see Section 9.2.5, "Single Instruction, Multiple Data (SIMD) Execution Model"). Packed Byte Integers 63 0 Packed Word Integers 63 0 Packed Doubleword Integers 63 0 Figure 9-3. Data Types Introduced with the MMX Technology 9.2.4 Memory Data Formats When stored in memory: bytes, words and doublewords in the packed data types are stored in consecutive addresses. The least significant byte, word, or doubleword is stored at the lowest address and the most significant byte, word, or doubleword is stored at the high address. The ordering of bytes, words, or doublewords in memory is always little endian. That is, the bytes with the low addresses are less significant than the bytes with high addresses. 9.2.5 Single Instruction, Multiple Data (SIMD) Execution Model MMX technology uses the single instruction, multiple data (SIMD) technique for performing arithmetic and logical operations on bytes, words, or doublewords packed into MMX registers (see Figure 9-4). For example, the PADDSW instruction adds 4 signed word integers from one source operand to...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.
- Winter '11