ia-32_volume1_basic-arch

Exception all use the vector 19 software exception

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Unformatted text preview: apped I/O ports.) There are two groups of I/O instructions: Those that transfer a single item (byte, word, or doubleword) between an I/O port and a general-purpose register Vol. 1 13-3 INPUT/OUTPUT Those that transfer strings of items (strings of bytes, words, or doublewords) between an I/O port and memory The register I/O instructions IN (input from I/O port) and OUT (output to I/O port) move data between I/O ports and the EAX register (32-bit I/O), the AX register (16-bit I/O), or the AL (8-bit I/O) register. The address of the I/O port can be given with an immediate value or a value in the DX register. The string I/O instructions INS (input string from I/O port) and OUTS (output string to I/O port) move data between an I/O port and a memory location. The address of the I/O port being accessed is given in the DX register; the source or destination memory address is given in the DS:ESI or ES:EDI register, respectively. When used with one of the repeat prefixes (such as REP), the INS and OUTS instructions perform string (or block) input or output operations. The repeat prefix REP modifies the INS and OUTS instructions to transfer blocks of data between an I/O port and memory. Here, the ESI or EDI register is incremented or decremented (according to the setting of the DF flag in the EFLAGS register) after each byte, word, or doubleword is transferred between the selected I/O port and memory. See the references for IN, INS, OUT, and OUTS in Chapter 3 and Chapter 4 of the Intel 64 and IA-32 Architectures Software Developer's Manual, Volumes 3A & 3B, for more information on these instructions. 13.5 PROTECTED-MODE I/O When the processor is running in protected mode, the following protection mechanisms regulate access to I/O ports: When accessing I/O ports through the I/O address space, two protection devices control access: -- The I/O privilege level (IOPL) field in the EFLAGS register -- The I/O permission bit map of a task state segment (TSS) When accessing memory-mapped I/O ports, the normal segmentation and paging protection and the MTRRs (in processors that support them) also affect access to I/O ports. See Chapter 4, "Protection," and Chapter 10, "Memory Cache Control," in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A, for a complete discussion of memory protection. The following sections describe the protection mechanisms available when accessing I/O ports in the I/O address space with the I/O instructions. 13.5.1 I/O Privilege Level In systems where I/O protection is used, the IOPL field in the EFLAGS register controls access to the I/O address space by restricting use of selected instructions. This protection mechanism permits the operating system or executive to set the priv- 13-4 Vol. 1 INPUT/OUTPUT ilege level needed to perform I/O. In a typical protection ring model, access to the I/O address space is restricted to privilege levels 0 and 1. Here, kernel and the device drivers are allowed to perform...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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