Unformatted text preview: d and the masked response of the processor when these conditions are detected. The Intel 64 and IA-32 Architectures Software Developer's Manual, Volumes 3A & 3B, list the floating-point exceptions that can be signaled for each floating-point instruction. 18.104.22.168 Invalid Operation Exception (#I) The processor reports an invalid operation exception in response to one or more invalid arithmetic operands. If the invalid operation exception is masked, the processor sets the IE flag and returns an indefinite value or a QNaN. This value overwrites the destination register specified by the instruction. If the invalid operation exception is not masked, the IE flag is set, a software exception handler is invoked, and the operands remain unaltered. See Section 22.214.171.124, "Using SNaNs and QNaNs in Applications," for information about the result returned when an exception is caused by an SNaN. The processor can detect a variety of invalid arithmetic operations that can be coded in a program. These operations generally indicate a programming error, such as dividing by . See the following sections for information regarding the invalidoperation exception when detected while executing x87 FPU or SSE/SSE2/SSE3 instructions: x87 FPU; Section 8.5.1, "Invalid Operation Exception" SIMD floating-point exceptions; Section 126.96.36.199, "Invalid Operation Exception (#I)" 188.8.131.52 Denormal Operand Exception (#D) The processor reports the denormal-operand exception if an arithmetic instruction attempts to operate on a denormal operand (see Section 184.108.40.206, "Normalized and Denormalized Finite Numbers"). When the exception is masked, the processor sets the DE flag and proceeds with the instruction. Operating on denormal numbers will produce results at least as good as, and often better than, what can be obtained when denormal numbers are flushed to zero. Programmers can mask this exception so that a computation may proceed, then analyze any loss of accuracy when the final result is delivered. When a denormal-operand exception is not masked, the DE flag is set, a software exception handler is invoked, and the operands remain unaltered. When denormal operands have reduced significance due to loss of low-order bits, it may be advisable to not operate on them. Precluding denormal operands from computations can be accomplished by an exception handler that responds to unmasked denormaloperand exceptions. 4-26 Vol. 1 DATA TYPES See the following sections for information regarding the denormal-operand exception when detected while executing x87 FPU or SSE/SSE2/SSE3 instructions: x87 FPU; Section 8.5.2, "Denormal Operand Exception (#D)" SIMD floating-point exceptions; Section 220.127.116.11, "Denormal-Operand Exception (#D)" 18.104.22.168 Divide-By-Zero Exception (#Z) The processor reports the floating-point divide-by-zero exception whenever an instruction attempts to divide a finite non-zero operand by 0. The masked response for the divid...
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- Winter '11
- X86, Intel corporation, 64-bit mode, fpu floating-point exception, FPU Control Instructions