Unformatted text preview: Pentium M, Intel Core Solo, Intel Core Duo, Intel Core 2 Duo processors Pentium with MMX Technology, Celeron, Pentium II, Pentium II Xeon, Pentium III, Pentium III Xeon, Pentium 4, Intel Xeon processors, Pentium M, Intel Core Solo, Intel Core Duo, Intel Core 2 Duo processors Pentium III, Pentium III Xeon, Pentium 4, Intel Xeon processors, Pentium M, Intel Core Solo, Intel Core Duo, Intel Core 2 Duo processors Pentium 4, Intel Xeon processors, Pentium M, Intel Core Solo, Intel Core Duo, Intel Core 2 Duo processors x87 FPU and SIMD State Management MMX Technology SSE Extensions SSE2 Extensions Vol. 1 5-1 INSTRUCTION SET SUMMARY Table 5-1. Instruction Groups and IA-32 Processors (Contd.)
Instruction Set Architecture SSE3 Extensions SSSE3 Extensions IA-32e mode: 64-bit mode instructions System Instructions VMX Instructions Intel 64 and IA-32 Processor Support Pentium 4 supporting HT Technology (built on 90nm process technology), Intel Core Solo, Intel Core Duo, Intel Core 2 Duo processors Intel Xeon processor 5100 series, Intel Core Solo, Intel Core Duo, Intel Core 2 Duo processors All Intel 64 processors All Intel 64 and IA-32 processors All Intel 64 and IA-32 processors supporting Intel Virtualization Technology The following sections list instructions in each major group and subgroup. Given for each instruction is its mnemonic and descriptive names. When two or more mnemonics are given (for example, CMOVA/CMOVNBE), they represent different mnemonics for the same instruction opcode. Assemblers support redundant mnemonics for some instructions to make it easier to read code listings. For instance, CMOVA (Conditional move if above) and CMOVNBE (Conditional move if not below or equal) represent the same condition. For detailed information about specific instructions, see the Intel 64 and IA-32 Architectures Software Developer's Manual, Volumes 3A & 3B. 5.1 GENERAL-PURPOSE INSTRUCTIONS The general-purpose instructions preform basic data movement, arithmetic, logic, program flow, and string operations that programmers commonly use to write application and system software to run on Intel 64 and IA-32 processors. They operate on data contained in memory, in the general-purpose registers (EAX, EBX, ECX, EDX, EDI, ESI, EBP, and ESP) and in the EFLAGS register. They also operate on address information contained in memory, the general-purpose registers, and the segment registers (CS, DS, SS, ES, FS, and GS). This group of instructions includes the data transfer, binary integer arithmetic, decimal arithmetic, logic operations, shift and rotate, bit and byte operations, program control, string, flag control, segment register operations, and miscellaneous subgroups. The sections that following introduce each subgroup. For more detailed information on general purpose-instructions, see Chapter 7, "Programming With General-Purpose Instructions." 5-2 Vol. 1 INSTRUCTION SET SUMMARY 5.1.1 Data Transfer Instructions The data transfer instructions move data betw...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.
- Winter '11