ia-32_volume1_basic-arch

Exceptions or setting flags in the eflags register 94

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Unformatted text preview: converts signed words into unsigned bytes, using unsigned saturation. 9.4.5 Unpack Instructions The PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ (unpack high-order data elements) instructions and the PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ (unpack low-order data elements) instructions unpack bytes, words, or doublewords from the high- or loworder data elements of the source and destination operands and interleave them in the destination operand. By placing all 0s in the source operand, these instructions can be used to convert byte integers to word integers, word integers to doubleword integers, or doubleword integers to quadword integers. Vol. 1 9-9 PROGRAMMING WITH INTEL MMXTM TECHNOLOGY 9.4.6 Logical Instructions PAND (bitwise logical AND), PANDN (bitwise logical AND NOT), POR (bitwise logical OR), and PXOR (bitwise logical exclusive OR) perform bitwise logical operations on the quadword source and destination operands. 9.4.7 Shift Instructions The logical shift left, logical shift right and arithmetic shift right instructions shift each element by a specified number of bit positions. The PSLLW/PSLLD/PSLLQ (shift packed data left logical) instructions and the PSRLW/PSRLD/PSRLQ (shift packed data right logical) instructions perform a logical left or right shift of the data elements and fill the empty high or low order bit positions with zeros. These instructions operate on packed words, doublewords, and quadwords. The PSRAW/PSRAD (shift packed data right arithmetic) instructions perform an arithmetic right shift, copying the sign bit for each data element into empty bit positions on the upper end of each data element. This instruction operates on packed words and doublewords. 9.4.8 EMMS Instruction The EMMS instruction empties the MMX state by setting the tags in x87 FPU tag word to 11B, indicating empty registers. This instruction must be executed at the end of an MMX routine before calling other routines that can execute floating-point instructions. See Section 9.6.3, "Using the EMMS Instruction," for more information on the use of this instruction. 9.5 COMPATIBILITY WITH X87 FPU ARCHITECTURE The MMX state is aliased to the x87 FPU state. No new states or modes have been added to IA-32 architecture to support the MMX technology. The same floating-point instructions that save and restore the x87 FPU state also handle the MMX state (for example, during context switching). MMX technology uses the same interface techniques between the x87 FPU and the operating system (primarily for task switching purposes). For more details, see Chapter 11, "Intel MMXTM Technology System Programming," in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A. 9-10 Vol. 1 PROGRAMMING WITH INTEL MMXTM TECHNOLOGY 9.5.1 MMX Instructions and the x87 FPU Tag Word After each MMX instruction, the entire x87 FPU tag word is set to valid (00B). The EMMS instruction (empty MMX state) sets the entire x87 FPU tag word to empty (11B). Chapter 11, "Intel MMXTM...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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