ia-32_volume1_basic-arch

Ia-32_volume1_basic-arch

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Unformatted text preview: s in 64-Bit Mode Register operands in 64-bit mode can be any of the following: 64-bit general-purpose registers (RAX, RBX, RCX, RDX, RSI, RDI, RSP, RBP, or R8-R15) 32-bit general-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP, or R8D-R15D) 16-bit general-purpose registers (AX, BX, CX, DX, SI, DI, SP, BP, or R8W-R15W) 8-bit general-purpose registers: AL, BL, CL, DL, SIL, DIL, SPL, BPL, and R8LR15L are available using REX prefixes; AL, BL, CL, DL, AH, BH, CH, DH are available without using REX prefixes. Segment registers (CS, DS, SS, ES, FS, and GS) RFLAGS register x87 FPU registers (ST0 through ST7, status word, control word, tag word, data operand pointer, and instruction pointer) MMX registers (MM0 through MM7) XMM registers (XMM0 through XMM15) and the MXCSR register Control registers (CR0, CR2, CR3, CR4, and CR8) and system table pointer registers (GDTR, LDTR, IDTR, and task register) Debug registers (DR0, DR1, DR2, DR3, DR6, and DR7) MSR registers RDX:RAX register pair representing a 128-bit operand 3.7.3 Memory Operands Source and destination operands in memory are referenced by means of a segment selector and an offset (see Figure 3-9). Segment selectors specify the segment containing the operand. Offsets specify the linear or effective address of the operand. Offsets can be 32 bits (represented by the notation m16:32) or 16 bits (represented by the notation m16:16). 15 Segment Selector 0 31 0 Offset (or Linear Address) Figure 3-9. Memory Operand Address 3.7.3.1 Memory Operands in 64-Bit Mode In 64-bit mode, a memory operand can be referenced by a segment selector and an offset. The offset can be 16 bits, 32 bits or 64 bits (see Figure 3-10). 3-28 Vol. 1 BASIC EXECUTION ENVIRONMENT 15 Segment Selector 0 63 Offset (or Linear Address) 0 Figure 3-10. Memory Operand Address in 64-Bit Mode 3.7.4 Specifying a Segment Selector The segment selector can be specified either implicitly or explicitly. The most common method of specifying a segment selector is to load it in a segment register and then allow the processor to select the register implicitly, depending on the type of operation being performed. The processor automatically chooses a segment according to the rules given in Table 3-5. When storing data in memory or loading data from memory, the DS segment default can be overridden to allow other segments to be accessed. Within an assembler, the segment override is generally handled with a colon ":" operator. For example, the following MOV instruction moves a value from register EAX into the segment pointed to by the ES register. The offset into the segment is contained in the EBX register: MOV ES:[EBX], EAX; Table 3-5. Default Segment Selection Rules Reference Type Instructions Stack Register Used CS SS Segment Used Code Segment Stack Segment Default Selection Rule All instruction fetches. All stack pushes and pops. Any memory reference which uses the ESP or EBP register as a base register. All data references, except when re...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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