ia-32_volume1_basic-arch

In an mmx register and stores the result in the low

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Unformatted text preview: of memory type aliasing is implementation specific. As one possible example, the memory type written to the bus may reflect the memory type for the first store to this line, as seen in program order; other alternatives are possible. This behavior should be considered reserved, and dependence on the behavior of any particular implementation risks future incompatibility. 10.4.6.3 PREFETCHh Instructions The PREFETCHh instructions permit programs to load data into the processor at a suggested cache level, so that the data is closer to the processor's load and store unit when it is needed. These instructions fetch 32 aligned bytes (or more, depending on the implementation) containing the addressed byte to a location in the cache hierarchy specified by the temporal locality hint (see Table 10-1). In this table, the firstlevel cache is closest to the processor and second-level cache is farther away from the processor than the first-level cache. The hints specify a prefetch of either temporal or non-temporal data (see Section 10.4.6.2, "Caching of Temporal vs. NonTemporal Data"). Subsequent accesses to temporal data are treated like normal accesses, while those to non-temporal data will continue to minimize cache pollution. If the data is already present at a level of the cache hierarchy that is closer to the processor, the PREFETCHh instruction will not result in any data movement. The PREFETCHh instructions do not affect functional behavior of the program. See Section 11.6.13, "Cacheability Hint Instructions," for additional information about the PREFETCHh instructions. Vol. 1 10-19 PROGRAMMING WITH STREAMING SIMD EXTENSIONS (SSE) Table 10-1. PREFETCHh Instructions Caching Hints PREFETCHh Instruction Mnemonic Actions PREFETCHT0 Temporal data--fetch data into all levels of cache hierarchy: Pentium III processor--1st-level cache or 2nd-level cache Pentium 4 and Intel Xeon processor--2nd-level cache Temporal data--fetch data into level 2 cache and higher Pentium III processor--2nd-level cache Pentium 4 and Intel Xeon processor--2nd-level cache Temporal data--fetch data into level 2 cache and higher Pentium III processor--2nd-level cache Pentium 4 and Intel Xeon processor--2nd-level cache Non-temporal data--fetch data into location close to the processor, minimizing cache pollution Pentium III processor--1st-level cache Pentium 4 and Intel Xeon processor--2nd-level cache PREFETCHT1 PREFETCHT2 PREFETCHNTA 10.4.6.4 SFENCE Instruction The SFENCE (Store Fence) instruction controls write ordering by creating a fence for memory store operations. This instruction guarantees that the result of every store instruction that precedes the store fence in program order is globally visible before any store instruction that follows the fence. The SFENCE instruction provides an efficient way of ensuring ordering between procedures that produce weakly-ordered data and procedures that consume that data. 10.5 FXSAVE AND FXRSTOR INSTRUCTIONS The FXSAVE and FXRST...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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