ia-32_volume1_basic-arch

Least significant byte of the result contains an even

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Unformatted text preview: ag The direction flag (DF, located in bit 10 of the EFLAGS register) controls string instructions (MOVS, CMPS, SCAS, LODS, and STOS). Setting the DF flag causes the string instructions to auto-decrement (to process strings from high addresses to low addresses). Clearing the DF flag causes the string instructions to auto-increment (process strings from low addresses to high addresses). The STD and CLD instructions set and clear the DF flag, respectively. 3-22 Vol. 1 BASIC EXECUTION ENVIRONMENT 3.4.3.3 System Flags and IOPL Field The system flags and IOPL field in the EFLAGS register control operating-system or executive operations. They should not be modified by application programs. The functions of the system flags are as follows: TF (bit 8) IF (bit 9) Trap flag -- Set to enable single-step mode for debugging; clear to disable single-step mode. Interrupt enable flag -- Controls the response of the processor to maskable interrupt requests. Set to respond to maskable interrupts; cleared to inhibit maskable interrupts. IOPL (bits 12 and 13) I/O privilege level field -- Indicates the I/O privilege level of the currently running program or task. The current privilege level (CPL) of the currently running program or task must be less than or equal to the I/O privilege level to access the I/O address space. This field can only be modified by the POPF and IRET instructions when operating at a CPL of 0. NT (bit 14) Nested task flag -- Controls the chaining of interrupted and called tasks. Set when the current task is linked to the previously executed task; cleared when the current task is not linked to another task. Resume flag -- Controls the processor's response to debug exceptions. Virtual-8086 mode flag -- Set to enable virtual-8086 mode; clear to return to protected mode without virtual-8086 mode semantics. Alignment check flag -- Set this flag and the AM bit in the CR0 register to enable alignment checking of memory references; clear the AC flag and/or the AM bit to disable alignment checking. Virtual interrupt flag -- Virtual image of the IF flag. Used in conjunction with the VIP flag. (To use this flag and the VIP flag the virtual mode extensions are enabled by setting the VME flag in control register CR4.) Virtual interrupt pending flag -- Set to indicate that an interrupt is pending; clear when no interrupt is pending. (Software sets and clears this flag; the processor only reads it.) Used in conjunction with the VIF flag. Identification flag -- The ability of a program to set or clear this flag indicates support for the CPUID instruction. RF (bit 16) VM (bit 17) AC (bit 18) VIF (bit 19) VIP (bit 20) ID (bit 21) For a detailed description of these flags: see Chapter 3, "Protected-Mode Memory Management," in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A. Vol. 1 3-23 BASIC EXECUTION ENVIRONMENT 3.4.3.4 RFLAGS Register in 64-Bit Mode In 64-bit mode, EFLAGS is extended to 64 bits and called RFLAGS. The upper 3...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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