Unformatted text preview: t significand available with the double extended-precision floating-point format of the x87 FPU data registers. This setting is best suited for most applications, because it allows applications to take full advantage of the maximum precision available with the x87 FPU data registers. Vol. 1 8-11 PROGRAMMING WITH THE X87 FPU Table 8-2. Precision Control Field (PC)
Precision Single Precision (24 bits) Reserved Double Precision (53 bits) Double Extended Precision (64 bits) PC Field 00B 01B 10B 11B The double precision and single precision settings reduce the size of the significand to 53 bits and 24 bits, respectively. These settings are provided to support IEEE Standard 754 and to provide compatibility with the specifications of certain existing programming languages. Using these settings nullifies the advantages of the double extended-precision floating-point format's 64-bit significand length. When reduced precision is specified, the rounding of the significand value clears the unused bits on the right to zeros. The precision-control bits only affect the results of the following floating-point instructions: FADD, FADDP, FIADD, FSUB, FSUBP, FISUB, FSUBR, FSUBRP, FISUBR, FMUL, FMULP, FIMUL, FDIV, FDIVP, FIDIV, FDIVR, FDIVRP, FIDIVR, and FSQRT. 184.108.40.206 Rounding Control Field The rounding-control (RC) field of the x87 FPU control register (bits 10 and 11) controls how the results of x87 FPU floating-point instructions are rounded. See Section 4.8.4, "Rounding," for a discussion of rounding of floating-point values; See Section 220.127.116.11, "Rounding Control (RC) Fields", for the encodings of the RC field. 8.1.6 Infinity Control Flag The infinity control flag (bit 12 of the x87 FPU control word) is provided for compatibility with the Intel 287 Math Coprocessor; it is not meaningful for later version x87 FPU coprocessors or IA-32 processors. See Section 18.104.22.168, "Signed Infinities," for information on how the x87 FPUs handle infinity values. 8.1.7 x87 FPU Tag Word The 16-bit tag word (see Figure 8-7) indicates the contents of each the 8 registers in the x87 FPU data-register stack (one 2-bit tag per register). The tag codes indicate whether a register contains a valid number, zero, or a special floating-point number (NaN, infinity, denormal, or unsupported format), or whether it is empty. The x87 FPU tag word is cached in the x87 FPU in the x87 FPU tag word register. When the x87 FPU is initialized with either an FINIT/FNINIT or FSAVE/FNSAVE instruction, the x87 FPU tag word is set to FFFFH, which marks all the x87 FPU data registers as empty. 8-12 Vol. 1 PROGRAMMING WITH THE X87 FPU . 15 TAG(7) TAG(6) TAG(5) TAG(4) TAG(3) TAG(2) TAG(1) 0 TAG(0) TAG Values 00 -- Valid 01 -- Zero 10 -- Special: invalid (NaN, unsupported), infinity, or denormal 11 -- Empty Figure 8-7. x87 FPU Tag Word
Each tag in the x87 FPU tag word corresponds to a physical register (numbers 0 through 7). The current top-of-stack (TOP) pointer stored in the x87 FPU...
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- Winter '11
- X86, Intel corporation, 64-bit mode, fpu floating-point exception, FPU Control Instructions