ia-32_volume1_basic-arch

Mode memory model 3 9 3 10 memory operands 64 bit

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Unformatted text preview: oarchitecture, 2-7 Pentium III Xeon processor description of, 2-4 Pentium M processor description of, 2-5 instructions supported, 2-5 Pentium Pro processor, 1-2 description of, 2-3 P6 family microarchitecture, 2-7 Pentium processor, 1-1 history of, 2-2 Pentium processor Extreme Edition introduction, 2-5 Pentium processor with MMX technology, 2-3 Performance monitoring counters, 3-5 PEXTRW instruction, 10-16 PF (parity) flag, EFLAGS register, 3-21, A-1 PHADDD instruction, 5-28, 12-11 PHADDSW instruction, 5-28, 12-11 PHADDW instruction, 5-28, 12-11 PHSUBD instruction, 5-29, 12-11 PHSUBSW instruction, 5-28, 12-11 PHSUBW instruction, 5-28, 12-11 Physical address space, 3-8 memory, 3-8 PINSRW instruction, 10-16 Pi, x87 FPU constant, 8-30 PM (inexact result exception) mask bit MXCSR register, 11-23 x87 FPU control word, 8-11, 8-43 PMADDUBSW instruction, 5-29, 12-12 PMADDWD instruction, 9-9 PMAXSW instruction, 10-17 PMAXUB instruction, 10-17 PMINSW instruction, 10-17 PMINUB instruction, 10-17 PMOVMSKB instruction, 10-17 PMULHRSW instruction, 5-29, 12-12 PMULHUW instruction, 10-17 PMULUDQ instruction, 11-15 Pointer data types, 4-8 Pointers 64-bit mode, 4-8 far pointer, 4-8 near pointer, 4-8 POP instruction, 6-1, 6-3, 7-8, 7-30 POPA instruction, 6-8, 7-8 POPF instruction, 3-20, 6-8, 7-29, 13-5 POPFD instruction, 3-20, 6-8, 7-29 POR instruction, 9-10 Power coordination, 2-6 PREFETCHh instructions, 10-19, 11-36 Privilege levels description of, 6-9 inter-privilege level calls, 6-8 protection rings, 6-9 stack switching, 6-15 Procedure calls description of, 6-5 far call, 6-5 for block-structured languages, 6-19 inter-privilege level call, 6-10 linking, 6-4 near call, 6-5 overview, 6-1 return instruction pointer (EIP register), 6-4 saving procedure state information, 6-8 stack, 6-1 stack switching, 6-10 to exception handler procedure, 6-14 to exception task, 6-17 to interrupt handler procedure, 6-14 to interrupt task, 6-17 to other privilege levels, 6-8 types of, 6-1 Processor identification earlier Intel architecture processors, 14-2 early processors, 14-2 notes on where to start, 14-1 using CPUID, 14-1 using CPUID instruction, 14-1 Processor state information, saving, 6-8 Protected mode I/O, 13-4 memory models used, 3-10 overview, 3-1 Protection rings, 6-9 PSADBW instruction, 10-17 PSHUFB instruction, 5-29, 12-12 PSHUFD instruction, 11-16 PSHUFHW instruction, 11-15 PSHUFLW instruction, 11-15 PSHUFW instruction, 10-17, 11-16 PSIGNB/W/D instruction, 5-30, 12-13 PSLLD instruction, 9-10 PSLLDQ instruction, 11-16 PSLLQ instruction, 9-10 PSLLW instruction, 9-10 PSRLDQ instruction, 11-16 Vol. 1 INDEX-11 INDEX PSUBB instruction, 9-8 PSUBD instruction, 9-8 PSUBQ instruction, 11-15 PSUBSB instruction, 9-8 PSUBSW instruction, 9-8 PSUBUSB instruction, 9-8 PSUBUSW instruction, 9-8 PSUBW instruction, 9-8 PUNPCKHBW instruction, 9-9 PUNPCKHDQ instruction, 9-9 PUNPCKHQDQ instruction, 11-16 PUNPCKHWD instruction, 9-9 PUNPCKLBW instruction, 9-9 PUNPCKLDQ instruction, 9-9 PUNPCKLQ...
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