ia-32_volume1_basic-arch

More information about stack structure in addition to

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Unformatted text preview: ecific registers (MSRs) -- The processor provides a variety of machine specific registers that are used to control and report on processor performance. Virtually all MSRs handle system related functions and are not accessible to an application program. One exception to this rule is the time-stamp counter. The MSRs are described in Appendix B, "Model-Specific Registers (MSRs)," of the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3B. Machine check registers -- The machine check registers consist of a set of control, status, and error-reporting MSRs that are used to detect and report on hardware (machine) errors. See Chapter 14, "Machine-Check Architecture," of the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A. Performance monitoring counters -- The performance monitoring counters allow processor performance events to be monitored. See Chapter 18, "Debugging and Performance Monitoring," in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3B. The remainder of this chapter describes the organization of memory and the address space, the basic program execution registers, and addressing modes. Refer to the Vol. 1 3-5 BASIC EXECUTION ENVIRONMENT following chapters in this volume for descriptions of the other program execution resources shown in Figure 3-1: x87 FPU registers -- See Chapter 8, "Programming with the x87 FPU." MMX Registers -- See Chapter 9, "Programming with Intel MMXTM Technology." XMM registers -- See Chapter 10, "Programming with Streaming SIMD Extensions (SSE)," Chapter 11, "Programming with Streaming SIMD Extensions 2 (SSE2)," and Chapter 12, "Programming with SSE3 and Supplemental SSE3." Stack implementation and procedure calls -- See Chapter 6, "Procedure Calls, Interrupts, and Exceptions." 3.2.1 64-Bit Mode Execution Environment The execution environment for 64-bit mode is similar to that described in Section 3.2. The following paragraphs describe the differences that apply. Address space -- A task or program running in 64-bit mode on an IA-32 processor can address linear address space of up to 264 bytes (subject to the canonical addressing requirement described in Section 3.3.7.1) and physical address space of up to 240 bytes. Software can query CPUID for the physical address size supported by a processor. Basic program execution registers -- The number of general-purpose registers (GPRs) available is 16. GPRs are 64-bits wide and they support operations on byte, word, doubleword and quadword integers. Accessing byte registers is done uniformly to the lowest 8 bits. The instruction pointer register becomes 64 bits. The EFLAGS register is extended to 64 bits wide, and is referred to as the RFLAGS register. The upper 32 bits of RFLAGS is reserved. The lower 32 bits of RFLAGS is the same as EFLAGS. See Figure 3-2. XMM registers -- There are 16 XMM data registers for SIMD operations. See Secti...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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