ia-32_volume1_basic-arch

Or tasks and for tasks operating in virtual 8086 mode

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Unformatted text preview: instruction will cause the invalid opcode exception (#UD) if executed on a processor that does not support it. To obtain processor identification information, a source operand value is placed in the EAX register to select the type of information to be returned. When the CPUID instruction is executed, selected information is returned in the EAX, EBX, ECX, and EDX registers. For a complete description of the CPUID instruction, tables indicating values returned, and example code, see "CPUID--CPUID Identification" in Chapter 3 of the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2A. 14.1.1 Notes on Where to Start For detailed application notes on the instruction, see AP-485, Intel Processor Identification and the CPUID Instruction (Order Number 241618). This publication provides additional information and example source code for use in identifying IA-32 processors. It also contains guidelines for using the CPUID instruction to help maintain the widest range of software compatibility. The following guidelines are among the most important, and should always be followed when using the CPUID instruction to determine available features: Always begin by testing for the "GenuineIntel," message in the EBX, EDX, and ECX registers when the CPUID instruction is executed with EAX equal to 0. If the processor is not genuine Intel, the feature identification flags may have different meanings than are described in Intel documentation. Vol. 1 14-1 PROCESSOR IDENTIFICATION AND FEATURE DETERMINATION Test feature identification flags individually and do not make assumptions about undefined bits. 14.1.2 Identification of Earlier IA-32 Processors The CPUID instruction is not available in earlier IA-32 processors up through the earlier Intel486 processors. For these processors, several other architectural features can be exploited to identify the processor. The settings of bits 12 and 13 (IOPL), 14 (NT), and 15 (reserved) in the EFLAGS register are different for Intel's 32-bit processors than for the Intel 8086 and Intel 286 processors. By examining the settings of these bits (with the PUSHF/PUSHFD and POP/POPFD instructions), an application program can determine whether the processor is an 8086, Intel 286, or one of the Intel 32-bit processors: 8086 processor -- Bits 12 through 15 of the EFLAGS register are always set. Intel 286 processor -- Bits 12 through 15 are always clear in real-address mode. 32-bit processors -- In real-address mode, bit 15 is always clear and bits 12 through 14 have the last value loaded into them. In protected mode, bit 15 is always clear, bit 14 has the last value loaded into it, and the IOPL bits depends on the current privilege level (CPL). The IOPL field can be changed only if the CPL is 0. Other EFLAG register bits that can be used to differentiate between the 32-bit processors: Bit 18 (AC) -- Implemented only on the Pentium 4, Intel Xeon, P6 family, Pentium, and Intel486 processors. The inability...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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