ia-32_volume1_basic-arch

Packed signed integers with signed saturation

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Unformatted text preview: Technology System Programming," in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A, provides additional information about the effects of x87 FPU and MMX instructions on the x87 FPU tag word. For a description of the tag word, see Section 8.1.7, "x87 FPU Tag Word." 9.6 WRITING APPLICATIONS WITH MMX CODE The following sections give guidelines for writing application code that uses MMX technology. 9.6.1 Checking for MMX Technology Support Before an application attempts to use the MMX technology, it should check that it is present on the processor. Check by following these steps: 1. Check that the processor supports the CPUID instruction by attempting to execute the CPUID instruction. If the processor does not support the CPUID instruction, this will generate an invalid-opcode exception (#UD). 2. Check that the processor supports the MMX technology (if CPUID.01H:EDX.MMX[bit 23] = 1). 3. Check that emulation of the x87 FPU is disabled (if CR0.EM[bit 2] = 0). If the processor attempts to execute an unsupported MMX instruction or attempts to execute an MMX instruction with CR0.EM[bit 2] set, this generates an invalid-opcode exception (#UD). Example 9-1 illustrates how to use the CPUID instruction to detect the MMX technology. This example does not represent the entire CPUID sequence, but shows the portion used for detection of MMX technology. Example 9-1. Partial Routine for Detecting MMX Technology with the CPUID Instruction ... ; identify existence of CPUID instruction ... ; identify Intel processor mov EAX, 1 ; request for feature flags CPUID ; 0FH, 0A2H CPUID instruction test EDX, 00800000H ; Is IA MMX technology bit (Bit 23 of EDX) set? jnz ; MMX_Technology_Found Vol. 1 9-11 PROGRAMMING WITH INTEL MMXTM TECHNOLOGY 9.6.2 Transitions Between x87 FPU and MMX Code Applications can contain both x87 FPU floating-point and MMX instructions. However, because the MMX registers are aliased to the x87 FPU register stack, care must be taken when making transitions between x87 FPU instructions and MMX instructions to prevent incoherent or unexpected results. When an MMX instruction (other than the EMMS instruction) is executed, the processor changes the x87 FPU state as follows: The TOS (top of stack) value of the x87 FPU status word is set to 0. The entire x87 FPU tag word is set to the valid state (00B in all tag fields). When an MMX instruction writes to an MMX register, it writes ones (11B) to the exponent part of the corresponding floating-point register (bits 64 through 79). The net result of these actions is that any x87 FPU state prior to the execution of the MMX instruction is essentially lost. When an x87 FPU instruction is executed, the processor assumes that the current state of the x87 FPU register stack and control registers is valid and executes the instruction without any preparatory modifications to the x87 FPU state. If the application contains both x87 FPU floating-point and MMX instructions, the following...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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