Unformatted text preview: single precision output QNaN1 is created from the double precision input SNaN as follows: the sign bit is preserved, the 11bit exponent 7FFH is replaced by the 8bit exponent FFH, and the 53bit significand is truncated to a 24bit significand by removing its 29 least significant bits. The second most significant bit of the significand is changed from 0 to 1 to convert the signaling NaN into a quiet NaN. E.4.2.3 Condition Codes, Exception Flags, and Response for Masked and Unmasked Numeric Exceptions In the following, the masked response is what the processor provides when a masked exception is raised by an SSE/SSE2/SSE3 numeric instruction. The same response is provided by the floatingpoint emulator for SSE/SSE2/SSE3 numeric instructions, when certain components of the quadruple input operands generate exceptions that are masked (the emulator also generates the correct answer, as specified by IEEE Standard 754 wherever applicable, in the case when no floatingpoint exception occurs). The unmasked response is what the emulator provides to the user handler for those components of the packed operands of SSE/SSE2/SSE3 instructions that raise unmasked exceptions. Note that for precomputation exceptions (floatingpoint E12 Vol. 1 GUIDELINES FOR WRITING SIMD FLOATINGPOINT EXCEPTION HANDLERS faults), no result is provided to the user handler. For postcomputation exceptions (floatingpoint traps), a result is provided to the user handler, as specified below. In the following tables, the result is denoted by 'res', with the understanding that for the actual instruction, the destination coincides with the first source operand (except for COMISS, UCOMISS, COMISD, and UCOMISD, whose destination is the EFLAGS register). Table E13. #I  Invalid Operations
Unmasked Response and Exception Code src1, src2 unchanged; #IA = 1 Instruction ADDPS ADDPD ADDSS ADDSD HADDPS HADDPD Condition src1 or src2 = SNaN
1 Masked Response Refer to Table E1 for NaN operands, #IA = 1 ADDSUBPS (the src1 = +Inf, src2 = Inf or addition src1 = Inf, src2 = +Inf component) ADDSUBPD (the addition component) SUBPS SUBPD SUBSS SUBSD HSUBPS HSUBPD src1 or src2 = SNaN res1 = QNaN Indefinite, #IA = 1 Refer to Table E1 for NaN operands, #IA = 1 src1, src2 unchanged; #IA = 1 ADDSUBPS (the src1 = +Inf, src2 = +Inf or subtraction src1 = Inf, src2 = Inf component) ADDSUBPD (the subtraction component) MULPS MULPD MULSS MULSD DIVPS DIVPD DIVSS DIVSD src1 or src2 = SNaN src1 = Inf, src2 = 0 or src1 = 0, src2 = Inf src1 or src2 = SNaN src1 = Inf, src2 = Inf or src1 = 0, src2 = 0 res = QNaN Indefinite, #IA = 1 Refer to Table E1 for NaN operands, #IA = 1 res = QNaN Indefinite, #IA = 1 Refer to Table E1 for NaN operands, #IA = 1 res = QNaN Indefinite, #IA = 1 src1, src2 unchanged; #IA = 1 src1, src2 unchanged; #IA = 1 Vol. 1 E13 GUIDELINES FOR WRITING SIMD FLOATINGPOINT EXCEPTION HANDLERS Table E13. #I  Invalid Operations (Contd.)
Unmasked Response and Exception Code src unchanged, #IA = 1 I...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.
 Winter '11
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