ia-32_volume1_basic-arch

Register and memory movhpd movlpd movmskpd movsd 5612

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Unformatted text preview: precision floating-point values to packed doubleword integers Convert with truncation packed double-precision floating-point values to packed doubleword integers Convert packed doubleword integers to packed double-precision floating-point values Convert packed single-precision floating-point values to packed double-precision floating-point values Convert packed double-precision floating-point values to packed single-precision floating-point values Convert scalar single-precision floating-point values to scalar double-precision floating-point values Convert scalar double-precision floating-point values to scalar single-precision floating-point values Convert scalar double-precision floating-point values to a doubleword integer Convert with truncation scalar double-precision floating-point values to scalar doubleword integers Convert doubleword integer to scalar double-precision floatingpoint value 5.6.2 SSE2 Packed Single-Precision Floating-Point Instructions SSE2 packed single-precision floating-point instructions perform conversion operations on single-precision floating-point and integer operands. These instructions represent enhancements to the SSE single-precision floating-point instructions. CVTDQ2PS CVTPS2DQ CVTTPS2DQ Convert packed doubleword integers to packed single-precision floating-point values Convert packed single-precision floating-point values to packed doubleword integers Convert with truncation packed single-precision floating-point values to packed doubleword integers 5.6.3 SSE2 128-Bit SIMD Integer Instructions SSE2 SIMD integer instructions perform additional operations on packed words, doublewords, and quadwords contained in XMM and MMX registers. MOVDQA MOVDQU MOVQ2DQ MOVDQ2Q Move aligned double quadword. Move unaligned double quadword Move quadword integer from MMX to XMM registers Move quadword integer from XMM to MMX registers 5-24 Vol. 1 INSTRUCTION SET SUMMARY PMULUDQ PADDQ PSUBQ PSHUFLW PSHUFHW PSHUFD PSLLDQ PSRLDQ PUNPCKHQDQ PUNPCKLQDQ Multiply packed unsigned doubleword integers Add packed quadword integers Subtract packed quadword integers Shuffle packed low words Shuffle packed high words Shuffle packed doublewords Shift double quadword left logical Shift double quadword right logical Unpack high quadwords Unpack low quadwords 5.6.4 SSE2 Cacheability Control and Ordering Instructions SSE2 cacheability control instructions provide additional operations for caching of non-temporal data when storing data from XMM registers to memory. LFENCE and MFENCE provide additional control of instruction ordering on store operations. CLFLUSH LFENCE MFENCE PAUSE MASKMOVDQU MOVNTPD MOVNTDQ MOVNTI Flushes and invalidates a memory operand and its associated cache line from all levels of the processor's cache hierarchy Serializes load operations Serializes load and store operations Improves the performance of "spin-wait loops" Non-temporal store of selected bytes from an XMM register into memory Non-temporal store of two pac...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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