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Unformatted text preview: xception. 4. Denormal-operand exception. If masked, then instruction execution continues and a lower-priority exception can occur as well. 5. Numeric overflow and underflow exceptions; possibly in conjunction with the inexact-result exception. 6. Inexact-result exception. Invalid operation, zero divide, and denormal operand exceptions are detected before a floating-point operation begins. Overflow, underflow, and precision exceptions are not detected until a true result has been computed. When an unmasked pre-operation exception is detected, the destination operand has not yet been updated, and appears as if the offending instruction has not been executed. When an unmasked post-operation exception is detected, the destination operand may be updated with a result, depending on the nature of the exception (except for SSE/SSE2/SSE3 instructions, which do not update their destination operands in such cases). 4.9.3 Typical Actions of a Floating-Point Exception Handler After the floating-point exception handler is invoked, the processor handles the exception in the same manner that it handles non-floating-point exceptions. The floating-point exception handler is normally part of the operating system or executive software, and it usually invokes a user-registered floating-point exception handle. A typical action of the exception handler is to store state information in memory. Other typical exception handler actions include: Examining the stored state information to determine the nature of the error Taking actions to correct the condition that caused the error Vol. 1 4-31 DATA TYPES Clearing the exception flags Returning to the interrupted program and resuming normal execution Increment in software an exception counter for later display or printing Print or display diagnostic information (such as the state information) Halt further program execution In lieu of writing recovery procedures, the exception handler can do the following: 4-32 Vol. 1 CHAPTER 5 INSTRUCTION SET SUMMARY
This chapter provides an abridged overview of Intel 64 and IA-32 instructions. Instructions are divided into the following groups: General purpose x87 FPU x87 FPU and SIMD state management Intel MMX technology SSE extensions SSE2 extensions SSE3 extensions SSSE3 extensions System instructions IA-32e mode: 64-bit mode instructions VMX instructions Table 5-1 lists the groups and IA-32 processors that support each group. Within these groups, most instructions are collected into functional subgroups. Table 5-1. Instruction Groups and IA-32 Processors
Instruction Set Architecture General Purpose x87 FPU Intel 64 and IA-32 Processor Support All Intel 64 and IA-32 processors Intel486, Pentium, Pentium with MMX Technology, Celeron, Pentium Pro, Pentium II, Pentium II Xeon, Pentium III, Pentium III Xeon, Pentium 4, Intel Xeon processors, Pentium M, Intel Core Solo, Intel Core Duo, Intel Core 2 Duo processors Pentium II, Pentium II Xeon, Pentium III, Pentium III Xeon, Pentium 4, Intel Xeon processors,...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.
- Winter '11