ia-32_volume1_basic-arch

See figure 6 9 the first doubleword holds a copy of

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: -purpose registers -- Eight 32-bit general-purpose registers (see Section 3.4.1, "General-Purpose Registers") are used in non-64-bit modes to address operands in memory. These registers are referenced by the names EAX, EBX, ECX, EDX, EBP, ESI EDI, and ESP. Segment registers -- The six 16-bit segment registers contain segment pointers for use in accessing memory (see Section 3.4.2, "Segment Registers"). These registers are referenced by the names CS, DS, SS, ES, FS, and GS. EFLAGS register -- This 32-bit register (see Section 3.4.3, "EFLAGS Register") is used to provide status and control for basic arithmetic, compare, and system operations. EIP register -- This 32-bit register contains the current instruction pointer (see Section 3.4.3, "EFLAGS Register"). General-purpose instructions operate on the following data types. The width of valid data types is dependent on processor mode (see Chapter 4): Bytes, words, doublewords Vol. 1 7-1 PROGRAMMING WITH GENERAL-PURPOSE INSTRUCTIONS Signed and unsigned byte, word, doubleword integers Near and far pointers Bit fields BCD integers 7.2 PROGRAMMING ENVIRONMENT FOR GP INSTRUCTIONS IN 64-BIT MODE The programming environment for the general-purpose instructions in 64-bit mode is similar to that described in Section 7.1. General-purpose registers -- In 64-bit mode, sixteen general-purpose registers available. These include the eight GPRs described in Section 7.1 and eight new GPRs (R8D-R15D). R8D-R15D are available by using a REX prefix. All sixteen GPRs can be promoted to 64 bits. The 64-bit registers are referenced as RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP and R8-R15 (see Section 3.4.1.1, "General-Purpose Registers in 64-Bit Mode"). Promotion to 64-bit operand requires REX prefix encodings. Segment registers -- In 64-bit mode, segmentation is available but it is set up uniquely (see Section 3.4.2.1, "Segment Registers in 64-Bit Mode"). Flags and Status register -- When the processor is running in 64-bit mode, EFLAGS becomes the 64-bit RFLAGS register (see Section 3.4.3, "EFLAGS Register"). Instruction Pointer register -- In 64-bit mode, the EIP register becomes the 64-bit RIP register (see Section 3.5.1, "Instruction Pointer in 64-Bit Mode"). General-purpose instructions operate on the following data types in 64-bit mode. The width of valid data types is dependent on default operand size, address size, or a prefix that overrides the default size: Bytes, words, doublewords, quadwords Signed and unsigned byte, word, doubleword, quadword integers Near and far pointers Bit fields Chapter 3, "Basic Execution Environment," for more information about IA-32e modes. Chapter 2, "Instruction Format," in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2A, for more detailed information about REX prefixes. Intel 64 and IA-32 Architectures Software Developer's Manual, Volumes 2A & 2B for a complet...
View Full Document

This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

Ask a homework question - tutors are online