ia-32_volume1_basic-arch

Segmentation is available but it is set up uniquely

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Unformatted text preview: er Memory location Segment register General-purpose register Memory location Segment register Memory location General-purpose register General-purpose register General-purpose register Segment register Segment register General-purpose register General-purpose register Control register Control register General-purpose register General-purpose register Debug register Debug register General-purpose register Immediate General-purpose register Immediate Memory location Immediate data to a register Immediate data to memory Table 7-2 shows mnemonics for CMOVcc instructions and the conditions being tested for each instruction. The condition code mnemonics are appended to the letters "CMOV" to form the mnemonics for CMOVcc instructions. The instructions listed in Table 7-2 as pairs (for example, CMOVA/CMOVNBE) are alternate names for the same instruction. The assembler provides these alternate names to make it easier to read program listings. CMOVcc instructions are useful for optimizing small IF constructions. They also help eliminate branching overhead for IF statements and the possibility of branch mispredictions by the processor. 7-4 Vol. 1 PROGRAMMING WITH GENERAL-PURPOSE INSTRUCTIONS These conditional move instructions are supported in the P6 family, Pentium 4, and Intel Xeon processors. Software can check if CMOVcc instructions are supported by checking the processor's feature information with the CPUID instruction. 7.3.1.2 Exchange Instructions The exchange instructions swap the contents of one or more operands and, in some cases, perform additional operations such as asserting the LOCK signal or modifying flags in the EFLAGS register. The XCHG (exchange) instruction swaps the contents of two operands. This instruction takes the place of three MOV instructions and does not require a temporary location to save the contents of one operand location while the other is being loaded. When a memory operand is used with the XCHG instruction, the processor's LOCK signal is automatically asserted. This instruction is thus useful for implementing semaphores or similar data structures for process synchronization. See "Bus Locking" in Chapter 7, "Multiple-Processor Management," of the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A, for more information on bus locking. The BSWAP (byte swap) instruction reverses the byte order in a 32-bit register operand. Bit positions 0 through 7 are exchanged with 24 through 31, and bit positions 8 through 15 are exchanged with 16 through 23. Executing this instruction twice in a row leaves the register with the same value as before. The BSWAP instruction is useful for converting between "big-endian" and "little-endian" data formats. This instruction also speeds execution of decimal arithmetic. (The XCHG instruction can be used to swap the bytes in a word.) Table 7-2. Conditional Move Instructions Instruction Mnemonic Unsigned Conditional Moves CMOVA/C...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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