ia-32_volume1_basic-arch

Space greater than 4 gbytes basic program execution

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Unformatted text preview: word integers. See Section 10.2, "SSE Programming Environment," for more information about these registers. Vol. 1 3-3 BASIC EXECUTION ENVIRONMENT Basic Program Execution Registers Address Space* 232 -1 Eight 32-bit Registers General-Purpose Registers Six 16-bit Registers 32-bits 32-bits FPU Registers Segment Registers EFLAGS Register EIP (Instruction Pointer Register) Eight 80-bit Registers Floating-Point Data Registers 0 *The address space can be flat or segmented. Using the physical address extension mechanism, a physical address space of 236 - 1 can be addressed. 16 bits 16 bits 16 bits 48 bits 48 bits MMX Registers Eight 64-bit Registers Control Register Status Register Tag Register Opcode Register (11-bits) FPU Instruction Pointer Register FPU Data (Operand) Pointer Register MMX Registers XMM Registers Eight 128-bit Registers XMM Registers 32-bits MXCSR Register Figure 3-1. IA-32 Basic Execution Environment for Non-64-bit Modes 3-4 Vol. 1 BASIC EXECUTION ENVIRONMENT Stack -- To support procedure or subroutine calls and the passing of parameters between procedures or subroutines, a stack and stack management resources are included in the execution environment. The stack (not shown in Figure 3-1) is located in memory. See Section 6.2, "Stacks," for more information about stack structure. In addition to the resources provided in the basic execution environment, the IA-32 architecture provides the following resources as part of its system-level architecture. They provide extensive support for operating-system and system-development software. Except for the I/O ports, the system resources are described in detail in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volumes 3A & 3B. I/O ports -- The IA-32 architecture supports a transfers of data to and from input/output (I/O) ports. See Chapter 13, "Input/Output," in this volume. Control registers -- The five control registers (CR0 through CR4) determine the operating mode of the processor and the characteristics of the currently executing task. See Chapter 2, "System Architecture Overview," in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A. Memory management registers -- The GDTR, IDTR, task register, and LDTR specify the locations of data structures used in protected mode memory management. See Chapter 2, "System Architecture Overview," in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A. Debug registers -- The debug registers (DR0 through DR7) control and allow monitoring of the processor's debugging operations. See Chapter 18, "Debugging and Performance Monitoring," in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3B. Memory type range registers (MTRRs) -- The MTRRs are used to assign memory types to regions of memory. See the sections on MTRRs in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3B. Machine sp...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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