Unformatted text preview: also apply to the use of MMX registers. An efficient interface to MMX routines might pass parameters and return values through the MMX registers or through a combination of memory locations (via the stack) and MMX registers. Do not use the EMMS instruction or mix MMX and x87 FPU code when using to the MMX registers to pass parameters. If a high-level language that does not support the MMX data types directly is used, the MMX data types can be defined as a 64-bit structure containing packed data types. When implementing MMX instructions in high-level languages, other approaches can be taken, such as: Passing parameters to an MMX routine by passing a pointer to a structure via the stack. Returning a value from a function by returning a pointer to a structure. Vol. 1 9-13 PROGRAMMING WITH INTEL MMXTM TECHNOLOGY 9.6.6 Using MMX Code in a Multitasking Operating System Environment An application needs to identify the nature of the multitasking operating system on which it runs. Each task retains its own state which must be saved when a task switch occurs. The processor state (context) consists of the general-purpose registers and the floating-point and MMX registers. Operating systems can be classified into two types: Cooperative multitasking operating system Preemptive multitasking operating system Cooperative multitasking operating systems do not save the FPU or MMX state when performing a context switch. Therefore, the application needs to save the relevant state before relinquishing direct or indirect control to the operating system. Preemptive multitasking operating systems are responsible for saving and restoring the FPU and MMX state when performing a context switch. Therefore, the application does not have to save or restore the FPU and MMX state. 9.6.7 Exception Handling in MMX Code MMX instructions generate the same type of memory-access exceptions as other IA-32 instructions (page fault, segment not present, and limit violations). Existing exception handlers do not have to be modified to handle these types of exceptions for MMX code. Unless there is a pending floating-point exception, MMX instructions do not generate numeric exceptions. Therefore, there is no need to modify existing exception handlers or add new ones to handle numeric exceptions. If a floating-point exception is pending, the subsequent MMX instruction generates a numeric error exception (interrupt 16 and/or assertion of the FERR# pin). The MMX instruction resumes execution upon return from the exception handler. 9.6.8 Register Mapping MMX registers and their tags are mapped to physical locations of the floating-point registers and their tags. Register aliasing and mapping is described in more detail in Chapter 11, "Intel MMXTM Technology System Programming," in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A. 9-14 Vol. 1 PROGRAMMING WITH INTEL MMXTM TECHNOLOGY 9.6.9 Effect of Instruction Prefixes on MMX Instructions Table 9-3 describes th...
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- Winter '11
- X86, Intel corporation, 64-bit mode, fpu floating-point exception, FPU Control Instructions