ia-32_volume1_basic-arch

That support additional operations on packed integer

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Unformatted text preview: M1 XMM0 0 Figure 10-2. XMM Registers SSE instructions use the XMM registers only to operate on packed single-precision floating-point operands. SSE2 extensions expand the functions of the XMM registers to operand on packed or scalar double-precision floating-point operands and packed 10-4 Vol. 1 PROGRAMMING WITH STREAMING SIMD EXTENSIONS (SSE) integer operands (see Section 11.2, "SSE2 Programming Environment," and Section 12.1, "SSE3/SSSE3 Programming Environment and Data types"). XMM registers can only be used to perform calculations on data; they cannot be used to address memory. Addressing memory is accomplished by using the generalpurpose registers. Data can be loaded into XMM registers or written from the registers to memory in 32-bit, 64-bit, and 128-bit increments. When storing the entire contents of an XMM register in memory (128-bit store), the data is stored in 16 consecutive bytes, with the low-order byte of the register being stored in the first byte in memory. 10.2.3 MXCSR Control and Status Register The 32-bit MXCSR register (see Figure 10-3) contains control and status information for SSE, SSE2, and SSE3 SIMD floating-point operations. This register contains: flag and mask bits for SIMD floating-point exceptions rounding control field for SIMD floating-point operations flush-to-zero flag that provides a means of controlling underflow conditions on SIMD floating-point operations denormals-are-zeros flag that controls how SIMD floating-point instructions handle denormal source operands The contents of this register can be loaded from memory with the LDMXCSR and FXRSTOR instructions and stored in memory with STMXCSR and FXSAVE. Bits 16 through 31 of the MXCSR register are reserved and are cleared on a powerup or reset of the processor; attempting to write a non-zero value to these bits, using either the FXRSTOR or LDMXCSR instructions, will result in a general-protection exception (#GP) being generated. Vol. 1 10-5 PROGRAMMING WITH STREAMING SIMD EXTENSIONS (SSE) 31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 F Z R C P U O Z D I D P U O Z D I A M M M M M M E E E E E E Z Reserved Flush to Zero Rounding Control Precision Mask Underflow Mask Overflow Mask Divide-by-Zero Mask Denormal Operation Mask Invalid Operation Mask Denormals Are Zeros* Precision Flag Underflow Flag Overflow Flag Divide-by-Zero Flag Denormal Flag Invalid Operation Flag * The denormals-are-zeros flag was introduced in the Pentium 4 and Intel Xeon processor. Figure 10-3. MXCSR Control/Status Register 10.2.3.1 SIMD Floating-Point Mask and Flag Bits Bits 0 through 5 of the MXCSR register indicate whether a SIMD floating-point exception has been detected. They are "sticky" flags. That is, after a flag is set, it remains set until explicitly cleared. To clear these flags, use the LDMXCSR or the FXRSTOR instruction to write zeroes to them. Bits 7 through 12 provide individual mask bits for the SIMD floating-point exceptions. An exception type is m...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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