ia-32_volume1_basic-arch

The processors instruction stream the next

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Unformatted text preview: logy support a single-instruction, multiple-data (SIMD) execution model that is designed to accelerate the performance of advanced media and communications applications. This chapter describes MMX technology. 9.1 OVERVIEW OF MMX TECHNOLOGY MMX technology defines a simple and flexible SIMD execution model to handle 64-bit packed integer data. This model adds the following features to the IA-32 architecture, while maintaining backwards compatibility with all IA-32 applications and operating-system code: Eight new 64-bit data registers, called MMX registers Three new packed data types: -- 64-bit packed byte integers (signed and unsigned) -- 64-bit packed word integers (signed and unsigned) -- 64-bit packed doubleword integers (signed and unsigned) Instructions that support the new data types and to handle MMX state management Extensions to the CPUID instruction MMX technology is accessible from all the IA32-architecture execution modes (protected mode, real address mode, and virtual 8086 mode). It does not add any new modes to the architecture. The following sections of this chapter describe MMX technology's programming environment, including MMX register set, data types, and instruction set. Additional instructions that operate on MMX registers have been added to the IA-32 architecture by the SSE/SSE2 extensions. For more information, see: Section 10.4.4, "SSE 64-Bit SIMD Integer Instructions," describes MMX instructions added to the IA-32 architecture with the SSE extensions. Section 11.4.2, "SSE2 64-Bit and 128-Bit SIMD Integer Instructions," describes MMX instructions added to the IA-32 architecture with SSE2 extensions. Intel 64 and IA-32 Architectures Software Developer's Manual, Volumes 2A & 2B, give detailed descriptions of MMX instructions. Vol. 1 9-1 PROGRAMMING WITH INTEL MMXTM TECHNOLOGY Chapter 11, "Intel MMXTM Technology System Programming," in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3B, describes the manner in which MMX technology is integrated into the IA-32 system programming model. 9.2 THE MMX TECHNOLOGY PROGRAMMING ENVIRONMENT Figure 9-1 shows the execution environment for MMX technology. All MMX instructions operate on MMX registers, the general-purpose registers, and/or memory as follows: MMX registers -- These eight registers (see Figure 9-1) are used to perform operations on 64-bit packed integer data. They are named MM0 through MM7. Address Space 232 MMX Registers Eight 64-Bit -1 General-Purpose Registers Eight 32-Bit 0 Figure 9-1. MMX Technology Execution Environment General-purpose registers -- The eight general-purpose registers (see Figure 3-5) are used with existing IA-32 addressing modes to address operands in memory. (MMX registers cannot be used to address memory). Generalpurpose registers are also used to hold operands for some MMX technology operations. They are EAX, EBX, ECX, EDX, EBP, ESI, EDI, and ESP. 9.2.1 MMX Technology in 64-Bit Mode and Compatibility Mod...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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