ia-32_volume1_basic-arch

Them one set at a time to an emulation function see

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Unformatted text preview: 0H or SNaN1 | 0008000000000000H2 SNaN | 00400000H or SNaN1 | 0008000000000000H2 QNaN QNaN Single precision or double precision QNaN Indefinite Unmasked Result None SNaN1 op QNaN2 None QNaN1 op SNaN2 QNaN1 op QNaN2 SNaN op real value None QNaN1 (not an exception) None Real value op SNaN None QNaN op real value Real value op QNaN Neither source operand is SNaN, but #I is signaled (e.g. for Inf Inf, Inf 0, Inf / Inf, 0/0) QNaN (not an exception) QNaN (not an exception) None NOTES: 1. For Tables E-1 to E-12: op denotes the operation to be performed. 2. SNaN | 0x00400000 is a quiet NaN in single precision format (if SNaN is in single precision) and SNaN | 0008000000000000H is a quiet NaN in double precision format (if SNaN is in double precision), obtained from the signaling NaN given as input. 3. Operations involving only quiet NaNs do not raise floating-point exceptions. E-8 Vol. 1 GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS Table E-2. CMPPS.EQ, CMPSS.EQ, CMPPS.ORD, CMPSS.ORD, CMPPD.EQ, CMPSD.EQ, CMPPD.ORD, CMPSD.ORD Source Operands NaN op Opd2 (any Opd2) Masked Result 00000000H or 0000000000000000H1 00000000H or 0000000000000000H1 Unmasked Result 00000000H or 0000000000000000H1 (not an exception) 00000000H or 0000000000000000H1 (not an exception) Opd1 op NaN (any Opd1) NOTE: 1. 32-bit results are for single, and 64-bit results for double precision operations. Table E-3. CMPPS.NEQ, CMPSS.NEQ, CMPPS.UNORD, CMPSS.UNORD, CMPPD.NEQ, CMPSD.NEQ, CMPPD.UNORD, CMPSD.UNORD Source Operands NaN op Opd2 (any Opd2) Masked Result FFFFFFFFH or FFFFFFFFFFFFFFFFH1 FFFFFFFFH or FFFFFFFFFFFFFFFFH1 Unmasked Result FFFFFFFFH or FFFFFFFFFFFFFFFFH1 (not an exception) FFFFFFFFH or FFFFFFFFFFFFFFFFH1 (not an exception) Opd1 op NaN (any Opd1) NOTE: 1. 32-bit results are for single, and 64-bit results for double precision operations. Table E-4. CMPPS.LT, CMPSS.LT, CMPPS.LE, CMPSS.LE, CMPPD.LT, CMPSD.LT, CMPPD.LE, CMPSD.LE Source Operands NaN op Opd2 (any Opd2) Opd1 op NaN (any Opd1) Masked Result 00000000H or 0000000000000000H1 00000000H or 0000000000000000H1 Unmasked Result None None NOTE: 1. 32-bit results are for single, and 64-bit results for double precision operations. Vol. 1 E-9 GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS Table E-5. CMPPS.NLT, CMPSS.NLT, CMPPS.NLE, CMPSS.NLE, CMPPD.NLT, CMPSD.NLT, CMPPD.NLE, CMPSD.NLE Source Operands NaN op Opd2 (any Opd2) Opd1 op NaN (any Opd1) Masked Result FFFFFFFFH or FFFFFFFFFFFFFFFFH1 FFFFFFFFH or FFFFFFFFFFFFFFFFH1 Unmasked Result None None NOTE: 1. 32-bit results are for single, and 64-bit results for double precision operations. Table E-6. COMISS, COMISD Source Operands SNaN op Opd2 (any Opd2) Opd1 op SNaN (any Opd1) QNaN op Opd2 (any Opd2) Opd1 op QNaN (any Opd1) Masked Result OF, SF, AF = 000 ZF, PF, CF = 111 OF, SF, AF = 000 ZF, PF, CF = 111 OF, SF, AF = 000 ZF, PF, CF = 111 OF, SF, AF = 000 ZF, PF, CF = 111 Unmasked Result None None None None Table E-7. UCOMISS, UCOMISD Source Operands SNaN...
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