ia-32_volume1_basic-arch

They are executed in 16 bit or 32 bit mode the

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Unformatted text preview: than one processor. Vol. 1 D-31 GUIDELINES FOR WRITING X87 FPU EXCEPTION HANDLERS D-32 Vol. 1 APPENDIX E GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS See Section 11.5, "SSE, SSE2, and SSE3 Exceptions," for a detailed discussion of SIMD floating-point exceptions. This appendix considers only SSE/SSE2/SSE3 instructions that can generate numeric (SIMD floating-point) exceptions, and gives an overview of the necessary support for handling such exceptions. This appendix does not address instructions that do not generate floating-point exceptions (such as RSQRTSS, RSQRTPS, RCPSS, or RCPPS), any x87 instructions, or any unlisted instruction. For detailed information on which instructions generate numeric exceptions, and a listing of those exceptions, refer to Appendix C, "Floating-Point Exceptions Summary." Non-numeric exceptions are handled in a way similar to that for the standard IA-32 instructions. E.1 TWO OPTIONS FOR HANDLING FLOATING-POINT EXCEPTIONS Just as for x87 FPU floating-point exceptions, the processor takes one of two possible courses of action when an SSE/SSE2/SSE3 instruction raises a floatingpoint exception: If the exception being raised is masked (by setting the corresponding mask bit in the MXCSR to 1), then a default result is produced which is acceptable in most situations. No external indication of the exception is given, but the corresponding exception flags in the MXCSR are set and may be examined later. Note though that for packed operations, an exception flag that is set in the MXCSR will not tell which of the sub-operands caused the event to occur. If the exception being raised is not masked (by setting the corresponding mask bit in the MXCSR to 0), a software exception handler previously registered by the user with operating system support will be invoked through the SIMD floatingpoint exception (#XF, vector 19). This case is discussed below in Section E.2, "Software Exception Handling." E.2 SOFTWARE EXCEPTION HANDLING The exception handling routine reached via interrupt vector 19 is usually part of the system software (the operating system kernel). Note that an interrupt descriptor table (IDT) entry must have been previously set up for this vector (refer to Chapter 5, Vol. 1 E-1 GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS "Interrupt and Exception Handling," in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A). Some compilers use specific run-time libraries to assist in floating-point exception handling. If any x87 FPU floating-point operations are going to be performed that might raise floating-point exceptions, then the exception handling routine must either disable all floating-point exceptions (for example, loading a local control word with FLDCW), or it must be implemented as re-entrant (for the case of x87 FPU exceptions, refer to Example D-1 in Appendix D, "Guidelines for Writing x87 FPU Exception Handlers")....
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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