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Unformatted text preview: urred. Normal power management protocol avoids this by going into power down states only after timed intervals in which no system activity occurs. D.3.6 Considerations When x87 FPU Shared Between Tasks The IA-32 architecture allows speculative deferral of floating-point state swaps on task switches. This feature allows postponing an x87 FPU state swap until an x87 FPU instruction is actually encountered in another task. Since kernel tasks rarely use floating-point, and some applications do not use floating-point or use it infrequently, the amount of time saved by avoiding unnecessary stores of the floating-point state is significant. Speculative deferral of x87 FPU saves does, however, place an extra burden on the kernel in three key ways: 1. The kernel must keep track of which thread owns the x87 FPU, which may be different from the currently executing thread. 2. The kernel must associate any floating-point exceptions with the generating task. This requires special handling since floating-point exceptions are delivered asynchronous with other system activity. 3. There are conditions under which spurious floating-point exception interrupts are generated, which the kernel must recognize and discard. Vol. 1 D-23 GUIDELINES FOR WRITING X87 FPU EXCEPTION HANDLERS D.3.6.1 Speculatively Deferring x87 FPU Saves, General Overview In order to support multitasking, each thread in the system needs a save area for the general-purpose registers, and each task that is allowed to use floating-point needs an x87 FPU save area large enough to hold the entire x87 FPU stack and associated x87 FPU state such as the control word and status word. (See Section 8.1.10, "Saving the x87 FPU's State with FSTENV/FNSTENV and FSAVE/FNSAVE," for a complete description of the x87 FPU save image.) If the processor and the operating system support Streaming SIMD Extensions, the save area should be large enough and aligned correctly to hold x87 FPU and Streaming SIMD Extensions state. On a task switch, the general-purpose registers are swapped out to their save area for the suspending thread, and the registers of the resuming thread are loaded. The x87 FPU state does not need to be saved at this point. If the resuming thread does not use the x87 FPU before it is itself suspended, then both a save and a load of the x87 FPU state has been avoided. It is often the case that several threads may be executed without any usage of the x87 FPU. The processor supports speculative deferral of x87 FPU saves via interrupt 7 "Device Not Available" (DNA), used in conjunction with CR0 bit 3, the "Task Switched" bit (TS). (See "Control Registers" in Chapter 2 of the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.) Every task switch via the hardware supported task switching mechanism (see "Task Switching" in Chapter 6 of the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A) sets TS. Multithreaded kernels t...
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- Winter '11