ia-32_volume1_basic-arch

To the user handler as specified below in the

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Unformatted text preview: ITING SIMD FLOATING-POINT EXCEPTION HANDLERS Table E-18. #P - Inexact Result (Precision) Instruction ADDPS ADDPD ADDSUBPS ADDSUBPD HADDPS HADDPD SUBPS SUBPD HSUBPS HSUBPD MULPS MULPD DIVPS DIVPD SQRTPS SQRTPD CVTDQ2PS CVTPI2PS CVTPS2PI CVTPS2DQ CVTPD2PI CVTPD2DQ CVTPD2PS CVTTPS2PI CVTTPD2PI CVTTPD2DQ CVTTPS2DQ ADDSS ADDSD SUBSS SUBSD MULSS MULSD DIVSS DIVSD SQRTSS SQRTSD CVTSI2SS CVTSS2SI CVTSD2SI CVTSD2SS CVTTSS2SI CVTTSD2SI Condition The result is not exactly representable in the destination format. Masked Response res = Result rounded to the destination precision and using the bounded exponent, but only if no unmasked underflow or overflow conditions occur (this exception can occur in the presence of a masked underflow or overflow); #PE = 1. Unmasked Response and Exception Code Only if no underflow/overflow condition occurred, or if the corresponding exceptions are masked: Set #OE if masked overflow and set result as described above for masked overflow. Set #UE if masked underflow and set result as described above for masked underflow. If neither underflow nor overflow, res equals the result rounded to the destination precision and using the bounded exponent set #PE = 1. E-20 Vol. 1 GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS E.4.3 Example SIMD Floating-Point Emulation Implementation The sample code listed below may be considered as being part of a user-level floating-point exception filter for the SSE/SSE2/SSE3 numeric instructions. It is assumed that the filter function is invoked by a low-level exception handler (reached via interrupt vector 19 when an unmasked floating-point exception occurs), and that it operates as explained in Section E.4.1, "Floating-Point Emulation." The sample code does the emulation only for the SSE instructions for addition, subtraction, multiplication, and division. For this, it uses C code and x87 FPU operations. Operations corresponding to other SSE/SSE2/SSE3 numeric instructions can be emulated similarly. The example assumes that the emulation function receives a pointer to a data structure specifying a number of input parameters: the operation that caused the exception, a set of sub-operands (unpacked, of type float), the rounding mode (the precision is always single), exception masks (having the same relative bit positions as in the MXCSR but starting from bit 0 in an unsigned integer), and flush-to-zero and denormals-are-zeros indicators. The output parameters are a floating-point result (of type float), the cause of the exception (identified by constants not explicitly defined below), and the exception status flags. The corresponding C definition is: typedef struct { unsigned int operation; //SSE or SSE2 operation: ADDPS, ADDSS, ... unsigned int operand1_uint32; //first operand value unsigned int operand2_uint32; //second operand value (if any) float result_fval; // result value (if any) unsigned int rounding_mode; //rounding mode unsigned int exc_masks; //exception masks, in the ord...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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