ia-32_volume1_basic-arch

Ia-32_volume1_basic-arch

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: he instruction using IA-32 double precision format, and the user's rounding mode; exceptions must have been disabled before calling this function; an inexact exception may be reported on the 53-bit fsubp, fmulp, or on both the 53-bit and 24-bit conversions, while an overflow or underflow (with traps disabled) may be reported on the conversion from dbl_res to res check whether there is an underflow, overflow, or inexact trap to be taken if the underflow traps are enabled and the result is tiny, take underflow trap if (!(exc_env->exc_masks & UNDERFLOW_MASK) && result_tiny) { dbl_res24 = TWO_TO_192 * dbl_res24; // exact exc_env->status_flag_underflow = 1; exc_env->exception_cause = UNDERFLOW; exc_env->result_fval = (float)dbl_res24; // exact if (sw & PRECISION_MASK) exc_env->status_flag_inexact = 1; return (RAISE_EXCEPTION); } // if overflow traps are enabled and the result is huge, take // overflow trap if (!(exc_env->exc_masks & OVERFLOW_MASK) && result_huge) { dbl_res24 = TWO_TO_M192 * dbl_res24; // exact exc_env->status_flag_overflow = 1; exc_env->exception_cause = OVERFLOW; exc_env->result_fval = (float)dbl_res24; // exact if (sw & PRECISION_MASK) exc_env->status_flag_inexact = 1; return (RAISE_EXCEPTION); } // set control word with rounding mode set to exc_env->rounding_mode, // double precision, and all exceptions disabled cw = cw | 0x0200; // set precision to double __asm { fldcw WORD PTR cw; } switch (exc_env->operation) { case ADDPS: case ADDSS: // perform the addition __asm { E-28 Vol. 1 GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS // load input operands fld DWORD PTR uiopd1; // may set the denormal status flag fld DWORD PTR uiopd2; // may set the denormal status flag faddp st(1), st(0); // rounded to 53 bits, may set the inexact // status flag // store result fstp QWORD PTR dbl_res; // exact, will not set any flag } break; case SUBPS: case SUBSS: // perform the subtraction __asm { // load input operands fld DWORD PTR uiopd1; // fld DWORD PTR uiopd2; // fsubp st(1), st(0); // // // store result fstp QWORD PTR dbl_res; } break; may set the denormal status flag may set the denormal status flag rounded to 53 bits, may set the inexact status flag // exact, will not set any flag case MULPS: case MULSS: // perform the multiplication __asm { // load input operands fld DWORD PTR uiopd1; // may set the denormal status flag fld DWORD PTR uiopd2; // may set the denormal status flag fmulp st(1), st(0); // rounded to 53 bits, exact // store result fstp QWORD PTR dbl_res; // exact, will not set any flag } break; case DIVPS: case DIVSS: // perform the division __asm { // load input operands fld DWORD PTR uiopd1; // may set the denormal status flag fld DWORD PTR uiopd2; // may set the denormal status flag fdivp st(1), st(0); // rounded to 53 bits, may set the inexact // status flag // store result fstp QWORD PTR dbl_res; // exact, will not set any flag } break; default: Vol. 1...
View Full Document

This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

Ask a homework question - tutors are online