ia-32_volume1_basic-arch

Using a byte mask to selectively write the individual

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Unformatted text preview: med. When a value is returned to the destination operand, it overwrites the destination register specified by the instruction. Table 11-1 lists the invalid-arithmetic operations that the processor detects for instructions and the masked responses to these operations. Table 11-1. Masked Responses of SSE/SSE2/SSE3 Instructions to Invalid Arithmetic Operations Condition ADDPS, ADDSS, ADDPD, ADDSD, SUBPS, SUBSS, SUBPD, SUBSD, MULPS, MULSS, MULPD, MULSD, DIVPS, DIVSS, DIVPD, DIVSD, ADDSUBPD, ADDSUBPD, HADDPD, HADDPS, HSUBPD or HSUBPS instruction with an SNaN operand SQRTPS, SQRTSS, SQRTPD, or SQRTSD with SNaN operands SQRTPS, SQRTSS, SQRTPD, or SQRTSD with negative operands (except zero) MAXPS, MAXSS, MAXPD, MAXSD, MINPS, MINSS, MINPD, or MINSD instruction with QNaN or SNaN operands CMPPS, CMPSS, CMPPD or CMPSD instruction with QNaN or SNaN operands Masked Response Return the SNaN converted to a QNaN; Refer to Table 4-7 for more details Return the SNaN converted to a QNaN Return the QNaN floating-point Indefinite Return the source 2 operand value Return a mask of all 0s (except for the predicates "not-equal," "unordered," "not-lessthan," or "not-less-than-or-equal," which returns a mask of all 1s) Return the SNaN converted to a QNaN Set EFLAGS values to "not comparable" Return the QNaN floating-point Indefinite Return the QNaN floating-point Indefinite Return the QNaN floating-point Indefinite CVTPD2PS, CVTSD2SS, CVTPS2PD, CVTSS2SD with SNaN operands COMISS or COMISD with QNaN or SNaN operand(s) Addition of opposite signed infinities or subtraction of like-signed infinities Multiplication of infinity by zero Divide of (0/0) or ( / ) 11-20 Vol. 1 PROGRAMMING WITH STREAMING SIMD EXTENSIONS 2 (SSE2) Table 11-1. Masked Responses of SSE/SSE2/SSE3 Instructions to Invalid Arithmetic Operations (Contd.) Condition Conversion to integer when the value in the source register is a NaN, , or exceeds the representable range for CVTPS2PI, CVTTPS2PI, CVTSS2SI, CVTTSS2SI, CVTPD2PI, CVTSD2SI, CVTPD2DQ, CVTTPD2PI, CVTTSD2SI, CVTTPD2DQ, CVTPS2DQ, or CVTTPS2DQ Masked Response Return the integer Indefinite If the invalid operation exception is not masked, a software exception handler is invoked and the operands remain unchanged. See Section 11.5.4, "Handling SIMD Floating-Point Exceptions in Software." Normally, when one or more of the source operands are QNaNs (and neither is an SNaN or in an unsupported format), an invalid-operation exception is not generated. The following instructions are exceptions to this rule: the COMISS and COMISD instructions; and the CMPPS, CMPSS, CMPPD, and CMPSD instructions (when the predicate is less than, less-than or equal, not less-than, or not less-than or equal). With these instructions, a QNaN source operand will generate an invalid-operation exception. The invalid-operation exception is not affected by the flush-to-zero mode or by the denormals-are-zeros mode. 11.5.2.2 Denormal-Operand Exce...
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