ia-32_volume1_basic-arch

Value to doubleword integer instruction is similar to

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Unformatted text preview: ve quadword integer from MMX to XMM registers) instruction moves the quadword integer from an MMX source register to an XMM destination register. The MOVDQ2Q (move quadword integer from XMM to MMX registers) instruction moves the low quadword integer from an XMM source register to an MMX destination register. 11.4.3 128-Bit SIMD Integer Instruction Extensions All of 64-bit SIMD integer instructions introduced with MMX technology and SSE extensions (with the exception of the PSHUFW instruction) have been extended by SSE2 extensions to operate on 128-bit packed integer operands located in XMM registers. The 128-bit versions of these instructions follow the same SIMD conventions regarding packed operands as the 64-bit versions. For example, where the 64-bit version of the PADDB instruction operates on 8 packed bytes, the 128-bit version operates on 16 packed bytes. 11.4.4 Cacheability Control and Memory Ordering Instructions SSE2 extensions that give programs more control over the caching, loading, and storing of data. are described below. 11-16 Vol. 1 PROGRAMMING WITH STREAMING SIMD EXTENSIONS 2 (SSE2) 11.4.4.1 FLUSH Cache Line The CLFLUSH (flush cache line) instruction writes and invalidates the cache line associated with a specified linear address. The invalidation is for all levels of the processor's cache hierarchy, and it is broadcast throughout the cache coherency domain. NOTE CLFLUSH was introduced with the SSE2 extensions. However, the instruction can be implemented in IA-32 processors that do not implement the SSE2 extensions. Detect CLFLUSH using the feature bit (if CPUID.01H:EDX.CLFSH[bit 19] = 1). 11.4.4.2 Cacheability Control Instructions The following four instructions enable data from XMM and general-purpose registers to be stored to memory using a non-temporal hint. The non-temporal hint directs the processor to store data to memory without writing the data into the cache hierarchy whenever this is possible. See Section 10.4.6.2, "Caching of Temporal vs. NonTemporal Data," for more information about non-temporal stores and hints. The MOVNTDQ (store double quadword using non-temporal hint) instruction stores packed integer data from an XMM register to memory, using a non-temporal hint. The MOVNTPD (store packed double-precision floating-point values using nontemporal hint) instruction stores packed double-precision floating-point data from an XMM register to memory, using a non-temporal hint. The MOVNTI (store doubleword using non-temporal hint) instruction stores integer data from a general-purpose register to memory, using a non-temporal hint. The MASKMOVDQU (store selected bytes of double quadword) instruction stores selected byte integers from an XMM register to memory, using a byte mask to selectively write the individual bytes. The memory location does not need to be aligned on a natural boundary. This instruction also uses a non-temporal hint. 11.4.4.3 Memory Ordering Instructions SSE2 extensions introduce two new fen...
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