Unformatted text preview: g of EFLAGS Status Flags for Floating-Point Number Comparisons
Comparison Results ST0 > ST(i) ST0 < ST(i) ST0 = ST(i) Unordered ZF 0 0 1 1 PF 0 0 0 1 CF 0 1 0 1 Software can check if the FCOMI and FCOMIP instructions are supported by checking the processor's feature information with the CPUID instruction. The FUCOMI and FUCOMIP instructions operate the same as the FCOMI and FCOMIP instructions, except that they do not generate a floating-point invalid-operation exception if the unordered condition is the result of one or both of the operands being a QNaN. The FCOMIP and FUCOMIP instructions pop the x87 FPU register stack following the comparison operation. The FXAM instruction determines the classification of the floating-point value in the ST(0) register (that is, whether the value is zero, a denormal number, a normal finite number, , a NaN, or an unsupported format) or that the register is empty. It sets the x87 FPU condition code flags to indicate the classification (see "FXAM--Examine" in Chapter 3, "Instruction Set Reference, A-M," of the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2A). It also sets the C1 flag to indicate the sign of the value. 220.127.116.11 Branching on the x87 FPU Condition Codes The processor does not offer any control-flow instructions that branch on the setting of the condition code flags (C0, C2, and C3) in the x87 FPU status word. To branch on the state of these flags, the x87 FPU status word must first be moved to the AX register in the integer unit. The FSTSW AX (store status word) instruction can be used for this purpose. When these flags are in the AX register, the TEST instruction can be used to control conditional branching as follows: 1. Check for an unordered result. Use the TEST instruction to compare the contents of the AX register with the constant 0400H (see Table 8-8). This operation will clear the ZF flag in the EFLAGS register if the condition code flags indicate an unordered result; otherwise, the ZF flag will be set. The JNZ instruction can then be used to transfer control (if necessary) to a procedure for handling unordered operands. 8-28 Vol. 1 PROGRAMMING WITH THE X87 FPU Table 8-8. TEST Instruction Constants for Conditional Branching
Order ST(0) > Source Operand ST(0) < Source Operand ST(0) = Source Operand Unordered Constant 4500H 0100H 4000H 0400H Branch JZ JNZ JNZ JNZ 2. Check ordered comparison result. Use the constants given in Table 8-8 in the TEST instruction to test for a less than, equal to, or greater than result, then use the corresponding conditional branch instruction to transfer program control to the appropriate procedure or section of code. If a program or procedure has been thoroughly tested and it incorporates periodic checks for QNaN results, then it is not necessary to check for the unordered result every time a comparison is made. See Section 8.1.4, "Branching and Conditional Moves on Condition Codes," for another tech...
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- Winter '11
- X86, Intel corporation, 64-bit mode, fpu floating-point exception, FPU Control Instructions