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Section 4.9.1, "FloatingPoint Exception Conditions," provides a general overview of how the IA32 processor detects and handles the 834 Vol. 1 PROGRAMMING WITH THE X87 FPU various classes of floatingpoint exceptions. This information pertains to x87 FPU as well as SSE/SSE2/SSE3 extensions. The following sections give specific information about how the x87 FPU handles floatingpoint exceptions that are unique to the x87 FPU. 8.4.1 Arithmetic vs. Nonarithmetic Instructions When dealing with floatingpoint exceptions, it is useful to distinguish between arithmetic instructions and nonarithmetic instructions. Nonarithmetic instructions have no operands or do not make substantial changes to their operands. Arithmetic instructions do make significant changes to their operands; in particular, they make changes that could result in floatingpoint exceptions being signaled. Table 89 lists the nonarithmetic and arithmetic instructions. It should be noted that some nonarithmetic instructions can signal a floatingpoint stack (fault) exception, but this exception is not the result of an operation on an operand. Table 89. Arithmetic and Nonarithmetic Instructions
Nonarithmetic Instructions FABS FCHS FCLEX FDECSTP FFREE FINCSTP FINIT/FNINIT FLD (registertoregister) FLD (extended format from memory) FLD constant FLDCW FLDENV FNOP FRSTOR FSAVE/FNSAVE FST/FSTP (registertoregister) FSTP (extended format to memory) FSTCW/FNSTCW FSTENV/FNSTENV Arithmetic Instructions F2XM1 FADD/FADDP FBLD FBSTP FCOM/FCOMP/FCOMPP FCOS FDIV/FDIVP/FDIVR/FDIVRP FIADD FICOM/FICOMP FIDIV/FIDIVR FILD FIMUL FIST/FISTP1 FISUB/FISUBR FLD (single and double) FMUL/FMULP FPATAN FPREM/FPREM1 FPTAN
Vol. 1 835 PROGRAMMING WITH THE X87 FPU Table 89. Arithmetic and Nonarithmetic Instructions (Contd.)
Nonarithmetic Instructions FSTSW/FNSTSW WAIT/FWAIT FXAM FXCH Arithmetic Instructions FRNDINT FSCALE FSIN FSINCOS FSQRT FST/FSTP (single and double) FSUB/FSUBP/FSUBR/FSUBRP FTST FUCOM/FUCOMP/FUCOMPP FXTRACT FYL2X/FYL2XP1 NOTE: 1. The FISTTP instruction in SSE3 is an arithmetic x87 FPU instruction. 8.5 X87 FPU FLOATINGPOINT EXCEPTION CONDITIONS The following sections describe the various conditions that cause a floatingpoint exception to be generated by the x87 FPU and the masked response of the x87 FPU when these conditions are detected. Intel 64 and IA32 Architectures Software Developer's Manual, Volumes 2A & 2B, list the floatingpoint exceptions that can be signaled for each floatingpoint instruction. See Section 4.9.2, "FloatingPoint Exception Priority," for a description of the rules for exception precedence when more than one floatingpoint exception condition is detected for an instruction. 8.5.1 Invalid Operation Exception The floatingpoint invalidoperation exception occurs in response to two subclasses of operations: Stack overflow or underflow (#IS) Invalid arithmetic operand (#IA) The flag for this exception (IE) is bit 0 of the x87...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.
 Winter '11
 Watlins

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