ia-32_volume1_basic-arch

X87 fpu state save x87 fpu state increment x87 fpu

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Unformatted text preview: instruction. NOTE Section 4.9.1, "Floating-Point Exception Conditions," provides a general overview of how the IA-32 processor detects and handles the 8-34 Vol. 1 PROGRAMMING WITH THE X87 FPU various classes of floating-point exceptions. This information pertains to x87 FPU as well as SSE/SSE2/SSE3 extensions. The following sections give specific information about how the x87 FPU handles floating-point exceptions that are unique to the x87 FPU. 8.4.1 Arithmetic vs. Non-arithmetic Instructions When dealing with floating-point exceptions, it is useful to distinguish between arithmetic instructions and non-arithmetic instructions. Non-arithmetic instructions have no operands or do not make substantial changes to their operands. Arithmetic instructions do make significant changes to their operands; in particular, they make changes that could result in floating-point exceptions being signaled. Table 8-9 lists the non-arithmetic and arithmetic instructions. It should be noted that some non-arithmetic instructions can signal a floating-point stack (fault) exception, but this exception is not the result of an operation on an operand. Table 8-9. Arithmetic and Non-arithmetic Instructions Non-arithmetic Instructions FABS FCHS FCLEX FDECSTP FFREE FINCSTP FINIT/FNINIT FLD (register-to-register) FLD (extended format from memory) FLD constant FLDCW FLDENV FNOP FRSTOR FSAVE/FNSAVE FST/FSTP (register-to-register) FSTP (extended format to memory) FSTCW/FNSTCW FSTENV/FNSTENV Arithmetic Instructions F2XM1 FADD/FADDP FBLD FBSTP FCOM/FCOMP/FCOMPP FCOS FDIV/FDIVP/FDIVR/FDIVRP FIADD FICOM/FICOMP FIDIV/FIDIVR FILD FIMUL FIST/FISTP1 FISUB/FISUBR FLD (single and double) FMUL/FMULP FPATAN FPREM/FPREM1 FPTAN Vol. 1 8-35 PROGRAMMING WITH THE X87 FPU Table 8-9. Arithmetic and Non-arithmetic Instructions (Contd.) Non-arithmetic Instructions FSTSW/FNSTSW WAIT/FWAIT FXAM FXCH Arithmetic Instructions FRNDINT FSCALE FSIN FSINCOS FSQRT FST/FSTP (single and double) FSUB/FSUBP/FSUBR/FSUBRP FTST FUCOM/FUCOMP/FUCOMPP FXTRACT FYL2X/FYL2XP1 NOTE: 1. The FISTTP instruction in SSE3 is an arithmetic x87 FPU instruction. 8.5 X87 FPU FLOATING-POINT EXCEPTION CONDITIONS The following sections describe the various conditions that cause a floating-point exception to be generated by the x87 FPU and the masked response of the x87 FPU when these conditions are detected. Intel 64 and IA-32 Architectures Software Developer's Manual, Volumes 2A & 2B, list the floating-point exceptions that can be signaled for each floating-point instruction. See Section 4.9.2, "Floating-Point Exception Priority," for a description of the rules for exception precedence when more than one floating-point exception condition is detected for an instruction. 8.5.1 Invalid Operation Exception The floating-point invalid-operation exception occurs in response to two sub-classes of operations: Stack overflow or underflow (#IS) Invalid arithmetic operand (#IA) The flag for this exception (IE) is bit 0 of the x87...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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