# Lab 4 - Jorge D Fernandez Engrd 230 Tuesday Section Lab 4...

• Lab Report
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Jorge D. Fernandez 03/12/2007 Engrd 230 Tuesday Section Lab 4: Designing an Arithmetic Logic Unit Purpose of the Lab: The purpose of this lab is to obtain more experience designing, implementing and testing an arithmetic unit. Design Overview: The design of the Arithmetic Logic Unit consisted of different parts that were made out of simple logic gates and MSI chips. The ALU was designed in such a way that if an operation was chosen the other ones would output a 0 8bit number. For instance, if Add was the operation chosen the output of Add would be the output gotten from the operation but all of the other ouputs, Sub, Slt, etc would produce a 0 8bit number. The parts were as follow: Decoder AddSubstract AndOr OutputAdd ShlShr Slt SevenSegment Below I will describe what each part does and how each part was implemented. Decoder: For the decoder I used the MSI chip 74138 which is a decoder whose outputs are active low. The purpose of the decoder is to identify the codes from the bus OP input and send the appropriate signal to perform the desired operation. Initially the decoder takes the OP signal which is divided into 3 wires to represent the 3 bits of the input. Those 3 wires (OP0, OP1, and OP2) go into input signals A[7..0], B[7..0] and C respectively. The active low enable signals of the decoder are attached to ground and the active high enable is attached to VCC. The input signals are then decoded and outputted in the corresponding outputs. For the Zero operation I chose output Y0N, for Add I chose Y1N, for Subtract I chose Y2N, for Slt I chose Y3N, for And I chose Y4N, for Or I chose Y5N, for Shift Left I chose Y6N and finally for Shift Right I chose Y7N. The Zero[7..0] output (Y0N) was connected to ground since the output had to be a 0 8bit number. All of the other outputs were inverted with a NOT gate since the outputs were active low and active high was needed. I then created a symbol for the decoder having input OP (bus signal) and outputs zero[7..0], add, sub, slt, and, or, shl and shr.

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• Spring '07
• ALBONESI/LONG
• Arithmetic logic unit, Most significant bit, INPUT VCC, Jorge D. Fernandez, SUM1 SUM2 SUM3

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