Lab 5 - Jorge D. Fernandez ENGRD 230 Lab Report Tuesday...

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Jorge D. Fernandez ENGRD 230 Lab Report Tuesday Section 04/02/2007 Up/Down Counter Lab Report Purpose of the Lab: The purpose of this lab was to gain knowledge and experience with the design, minimization and implementation of sequential circuits. Design Overview The design consisted of four smaller sequential circuits that represented each of the four bits, four d flip-flops and the given inputs and outputs. The four smaller sequential circuits were named nextq0, nextq1, nextq3 and nextq4 with the last one representing the most significant bit. Each of the four sequential circuits was derived and minimized from equations obtained by using truth tables. The designs of each of the four sequential circuits are as followed: Nextq0 This sequential circuit outputted the least significant bit of the up/down counter design. It took the input Mode (with 1 representing counting by 3 and 0 representing counting by one) and inputs QA, QB, QC and QD (with QA representing the least significant bit of the previous output and QD representing the most significant bit). It did not need an Up/down input since it increased and decreased by the same factor on both modes. Each of the five inputs is NANded with the corresponding inputs described in the equation obtained from the truth tables. Only NAND gates are used. The NOT gate was substituted by a NAND gate taking a single input twice and outputting the NOT version of that input. The equation for Mode 0 was QA’+QD*QB+QC*QD. The one for Mode 1 was QD*QB*QC+QA’. Nextq1 This sequential circuit outputted the second least significant bit of the up/down counter design. It took the input Mode (with 1 representing counting by 3 and 0 representing counting by one), input Up/Dow (with 0 representing the down count and 1 representing the up count) and inputs QA, QB, QC and QD (with QA representing the least significant bit of the previous output and QD representing the most significant bit). Each of the five inputs is NANded with the corresponding inputs described in the equation obtained from the truth tables. Only NAND gates are used. The NOT gate was substituted by a NAND gate taking a single input twice and outputting the NOT version of that input. The equation for Mode 0 was Up/Down’*QA*QB*QD’+QA’*QB’*QD’*QC*Up/Down’+ QD*QC’*QB’*QA’*Up/Down’+ QB’*QA*QD’*Up/Down+ QD’*QB*QA’*Up/Down. The equation for Mode 1 was QD’*QC’*QB’*QA’+ QC*QB’*QA*Up/Down’+
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QD*QB’*QA*Up/Down’+ QD*QC*QA+ QD*QC*QB+ QC*QB*QA’*Up/Down’+ QD*QB*QA’*Up/Down’+ QA’*QB’*QD’*Up/Down+ QA’*QB’*QD*QC’*Up/Down+ QB*QA*QC*Up/Down+ QB*QA*QD’*Up/Down. Nextq2
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This lab report was uploaded on 09/26/2007 for the course ENGRD 2300 taught by Professor Albonesi/long during the Spring '07 term at Cornell University (Engineering School).

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Lab 5 - Jorge D. Fernandez ENGRD 230 Lab Report Tuesday...

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