Lab 6 - Jorge D Fernandez ENGRD 230-Lab Tuesday Section LCD...

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Jorge D. Fernandez ENGRD 230-Lab 04/19/2007 Tuesday Section LCD Display Purpose of the Lab: The purpose of this lab was to gain knowledge and experience with the design, minimization and implementation of sequential circuits. In this specific case, gain experience with DE2 boards. Design Overview: This design consisted of two separate sequential circuits (state machines) that accounted for the two different messages to be displayed. That is, two identical state machines in which one of two different messages was displayed. The final design, in which the operations were defined, was composed of a regular combinational circuit that combined the two identical state machines. The whole design was made up of two parts. The first part was the lcddisplay1, which consisted of the sequential design that accounted for the first message to be displayed. The second part was an identical sequential circuit, lcddisplay2, which accounted for the second message. Each of the lcddisplay sequential circuits was broken down into counters, flip-flops and logic gates. Each one had a 1.6 milli seconds counter, .32 micro seconds counter, 38 counter, 4 D flip-flops, logic gates and the LCD_LUT given in the lab. The designs for the different parts are as follow: 38 counter This counter’s purpose was to count up to 38 to indicate when the message contained in the LCD_LUT was completely sent to the display. Each of the counts was followed by a series of five steps in which each character of the message contained in the LCD_LUT was sent to the display. This 38 counter was coded and developed in Verilog. Its symbol was created after compiling the Verilog code. 1.6 ms counter This counter’s purpose was to count up to 1.6 milliseconds to create the time delay needed for the LCD module to execute a command or display a character. Every time after 1.6 milliseconds the counter indicated that the LCD module was done executing a command or displaying a character. The 1.6 milliseconds counter was coded and developed in Verilog. It was made by counting the clock cycles until 1.6 milliseconds passed. Since the there were 50M clock cycles per second, 80000 clock cycles had to be counted to create a time delay of 1.6 milliseconds.
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.32 μs counter This counter’s purpose was to count up to .32 microseconds to create the time delay needed for the LCD module to read its inputs. Every time after .32 microseconds the counter indicated that the LCD module was done reading its inputs. The .32 microseconds counter was coded and developed in Verilog. It was made by counting the clock cycles until .32 microseconds passed. Since the there were 50M clock cycles per second, 16 clock cycles had to be counted to create a time delay of .32 microseconds.
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