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Unformatted text preview: sign the circuit, by specifying values for
(8 points) and , such that Sketch the dc load line and plot the Q-point. (6 points) = 0.25 mA/V2 and The parameters for the transistor are Solution
⁄( The voltage drop across
is 4 V, so that
operating in the saturation region. Then
[ . Assume the transistor is ( [ , since the other solution has
FET is off. The gate current is zero so that
below. ( , which implies the
. Thus, ( (
so that the transistor is indeed in saturation. The dc load line is shown 19 55:041 Electronic Circuits. The University of Iowa. Fall 2011. Problem 17 Consider the circuit below. The characteristics for the FET are also shown. In the
(b) Write the dc load line equation for the FET (2 points)
(c) Draw the dc load line equation on the FET characteristics, indicating the Q-point.
(d) Is the FET operating in the saturation region? (2 points) Solution
Part (a) No gate current flows, so
Part (b) ( ⁄ Part (d) The Q-point is where the dc load line intercepts the FET characteristics with
For the figure is it clear the FET in not operating in the saturation region.
20 . 55:041 Electronic Circuits. The University of Iowa. Fall 2011. Problem 18 The transistor characteristics for an NMOS FET are shown below.
(a) Is this an enhancement- or depletion-mode device? (2 points)
(b) Estimate a value for
. (6 points)...
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This note was uploaded on 10/26/2013 for the course ECE 55:041 taught by Professor Kruger during the Fall '11 term at University of Iowa.
- Fall '11