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Line 38: RA = ½ * (58-5C) = -2
Line 38: D7FE
30 3. What happens to the fetch3.
execute pipeline when
branching/calling 31 Branch/Subroutine Instruction Timing
• Branch instructions are those that
change the program counter (PC) (i.e.,
all branching and call instructions)
• Since the fetch stage incorrectly gets
the machine code for the next
sequential instruction when branching,
this machine code must be dumped.
this 32 bra Instruction in Data Sheet
instruction must be
• Nothing can be
executed in the
second 33 Branch/Subroutine Instruction Timing
• This dumping results in taken branches
(including unconditional branches)
requiring two instruction clocks to
• Branches that are not taken require only
one machine cycle.
one 34 Using Program Loops to Create Time Delays
• Consider the following code fragment:
DelayLoop: decfsz DELAY_L
bra • Because the DELAY_L register is 8-bit,
the loop can be repeated a maximum of
• How do we get a longer delay?
• Solution: Looping within a loop or
35 Using Program Loops to Create Time Delays
• e.g., DELAY_L = 0x00, DELAY_H = 0x02
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- Fall '13