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Unformatted text preview: ECE 315 Final Exam Solution Fall 2005 1. A uniformly doped semiconductor ( N A = 10 17 cm3 ) sandwiched between two metal electrodes has an area of 100 m 2 and a thickness of 50nm. The electrodes have good Ohmic contacts with the semiconductor. Assume n i =10 10 cm3 , si =11.7, n =1,000cm 2 /Vs, p =400cm 2 /Vs, and n = p =107 s. The semiconductor can be viewed as a resistor (when the carriers can respond to the signal from the electrodes quasistatically) and a capacitor (when the semiconductor can be treated as a dielectric) in parallel. Calculate this RC time constant. (5 pts) Above what frequency will the semiconductor behave more like a capacitor than a resistor? (2 pts) ( Hint: You do not need to use all numbers given above, and the time constant here is called the dielectric relaxation time ) We get RC = 0.16ps . The frequency when the slab will behave more like a capacitor than resistor will be at f=1/RC = 6.2THz , which is very high in todays electronic applications. Notice that the expression is a material constant once the doping is known. This RC number is called the dielectric relaxation time, which governs how fast a signal can propagate in a conductor. 2. For a pMOSFET with an ntype substrate doping, will the source and drain doping be (circle one) (a): ntype, (b): ptype or (c): unable to determine? (2 pts) When the hole concentrations p at the source end x=x 1 and the drain end x=x 2 cut lines as indicated below, give the operating conditions of V GS and V DS (with respect to V th ), and the operating regions (below V th , above V th linear, and above V th saturation), respectively. (6 pts) Notice that V th is defined by V GS in inversion and is negative here. PMOSFET has ptype source and drain regions (heavily doped), and the body can be either ntype (enhancement mode) or ptype (depletion mode). Remember that V GS needs to be more negative than V th to turn on the PMOS. N A =10 17 cm3 , N =0 50nm p A si si p A q N R C l A C A q N l A l R = = = = N D doping n = N D p = n i 2 /N D y y p y At x 1 At x 2 S D G x x=x 1 x=x 2 y y At x 1 At x 2 y y At x 1 At x 2 n p Region: above V th linear V GS : < V th V DS > V GS V th Region: below V th V GS : > V th V DS : not sure, Region: above V th saturation V GS : < V th V DS < V GS V th 1 3. For a bipolar pn junction as shown below ( N D > N A ) with the depletion region approximation, draw the required net charge , electric field F , electrostatic potential , electron concentration n , hole concentration p , electron current density J n and hole current density J p . (a) Under the equilibrium condition, i.e., V A =0V. Use solid line on the plot below. (7 pts) (b) Under V A =0.5V. Use dashed lines on the same plots, showing the relative position with the plots in (a) (7 pts) 4. Sketch a CMOS logic circuit that realizes the logic function of Y=ABC+ABC , which is the equivalence function....
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This note was uploaded on 02/10/2008 for the course ECE 2200 taught by Professor Johnson during the Fall '05 term at Cornell University (Engineering School).
 Fall '05
 JOHNSON

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