2--x86 Processor

2-x86 Processor

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Unformatted text preview: PU and memory. The I/O bus transfers data between the CPU and the system input/output devices. The control bus uses binary signals to synchronize actions of all devices attached to the system bus. The address bus holds the addresses of instructions and data when the currently executing instruction transfers data between the CPU and memory. Clock Each operation involving the CPU and the system bus is synchronized by an internal clock pulsing at a constant rate. The basic unit of time for machine instructions is a machine cycle (or clock cycle). The length of a clock cycle is the time required for one complete clock pulse. In the following figure, a clock cycle is depicted as the time between one falling edge and the next: one cycle 1 0 The duration of a clock cycle is calculated as the reciprocal of the clock’s speed, which in turn is measured in oscillations per second. A clock that oscillates 1 billion times per second (1 GHz), for example, produces a clock cycle with a duration of one billionth of a second (1 nanosecond). A machine instruction requires at least one clock cycle to execute, and a few require in excess of 50 clocks (the multiply instruction on the 8088 processor, for example). Instructions requiring memory access often have empty clock cycles called wait states because of the differences in the speeds of the CPU, the system bus, and memory circuits. 2.1.2 Instruction Execution Cycle The execution of a single machine instruction can be divided into a sequence of individual operations called the instruction execution cycle. Before executing, a program is loaded into memory. The instruction pointer contains the address of the next instruction. The instruction queue holds a group of instructions about to be executed. Executing a machine instruction requires three basic steps: fetch, decode, and execute. Two more steps are required when the instruction uses a memory operand: fetch operand and store output operand. Each of the steps is described as follows: • Fetch: The control unit fetches the next instruction from the instruction queue and increments the inst...
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This note was uploaded on 11/29/2013 for the course CSE 451 taught by Professor Hussein during the Winter '13 term at Fatih Üniversitesi.

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