2--x86 Processor

The ip is also known as the program counter decode

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Unformatted text preview: ruction pointer (IP). The IP is also known as the program counter. • Decode: The control unit decodes the instruction’s function to determine what the instruction will do. The instruction’s input operands are passed to the ALU, and signals are sent to the ALU indicating the operation to be performed. • Fetch operands: If the instruction uses an input operand located in memory, the control unit uses a read operation to retrieve the operand and copy it into internal registers. Internal registers are not visible to user programs. For More BS-IT Books, Notes & Assignments visit: www.bsit.zxq.net Chapter 2 • x86 Downloaded From: www.bsit.zxq.net Processor Architecture 32 • Execute: The ALU executes the instruction using the named registers and internal registers as operands and sends the output to named registers and/or memory. The ALU updates status flags providing information about the processor state. • Store output operand: If the output operand is in memory, the control unit uses a write operation to store the data. The sequence of steps can be expressed neatly in pseudocode: loop fetch next instruction advance the instruction pointer (IP) decode the instruction if memory operand needed, read value from memory execute the instruction if result is memory operand, write result to memory continue loop A block diagram showing data flow within a typical CPU is shown in Figure 2–2. The diagram helps to show relationships between components that interact during the instruction execution cycle. In order to read program instructions from memory, an address is placed on the address bus. Next, the memory controller places the requested code on the data bus, making the code available inside the code cache. The instruction pointer’s value determines which instruction will be executed next. The instruction is analyzed by the instruction decoder, causing the appropriate Code Data Address bus Memory Data bus Figure 2–2 Simplified CPU Block Diagram. Code cache Instruction pointer Instruction decoder Control unit Floating-point unit Registers ALU Data cache For More...
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This note was uploaded on 11/29/2013 for the course CSE 451 taught by Professor Hussein during the Winter '13 term at Fatih Üniversitesi.

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