2--x86 Processor

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Unformatted text preview: BS-IT Books, Notes & Assignments visit: www.bsit.zxq.net 2.1 General Concepts Downloaded From: www.bsit.zxq.net 33 digital signals to be sent to the control unit, which coordinates the ALU and floating-point unit. Although the control bus is not shown in this figure, it carries signals that use the system clock to coordinate the transfer of data between the different CPU components. 2.1.3 Reading from Memory Program throughput is often dependent on the speed of memory access. CPU clock speed might be several gigahertz, whereas access to memory occurs over a system bus running at a much slower speed. The CPU must wait one or more clock cycles until operands have been fetched from memory before the current instruction can complete its execution. The wasted clock cycles are called wait states. Several steps are required when reading instructions or data from memory, controlled by the processor’s internal clock. Figure 2–3 shows the processor clock (CLK) rising and falling at regular time intervals. In the figure, a clock cycle begins as the clock signal changes from high to low. The changes are called trailing edges, and they indicate the time taken by the transition between states. Figure 2–3 Memory Read Cycle. Cycle 1 Cycle 2 Cycle 3 Cycle 4 CLK Address ADDR RD Data DATA The following is a simplified description of what happens during each clock cycle during a memory read: Cycle 1: The address bits of the memory operand are placed on the address bus (ADDR). The address lines in the diagram cross, showing that some bits equal 1 and others equal 0. Cycle 2: The read line (RD) is set low (0) to notify memory that a value is to be read. Cycle 3: The CPU waits one cycle to give memory time to respond. During this cycle, the memory controller places the operand on the data bus (DATA). Cycle 4: The read line goes to 1, signaling the CPU to read the data on the data bus. For More BS-IT Books, Notes & Assignments visit: www.bsit.zxq.net 34 Chapter 2 • x86 Downloaded From: www.bsit.zxq.net Processor Architecture Cache Memory Because conventional memory is so much slower than the CPU, computers use high-speed cache m...
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This note was uploaded on 11/29/2013 for the course CSE 451 taught by Professor Hussein during the Winter '13 term at Fatih Üniversitesi.

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