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Unformatted text preview: nsist of two cascaded BCD stages and each one is driven by its own
clock signal. When the counter select line is HIGH, the outputs of counter 1 will
be allowed to pass through the multiplexers to the decoder/drivers to be
displayed on the LED readouts. When the COUNTER SELECT =0, the outputs of
counter 2 will pass through the multiplexers to the displays. VLSI
VLSI DESIGN AND IMPLEMENTATION
OF ENCODER & DECODER USING VHDL
I n this project of “VLSI design and implementation of E ncoder & Decoder using
VHDL ” we design a complex digital circuit using the language V HDL (V ery High
Speed Integrated Circuit Hardware Description Language).
As it is not possible to design such a complex digital circuit (consisting of more
than 30,000 logic gates) manually to implement the above application, we use
VLSI Technology for the solution. With this technology we can construct a very
big digital circuit requiring more than one lakh logic gates in a single chip .
This is carried out (Designed) by Programming. Thus it is simple and easy to
modify the existing desig...
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- Fall '12
- Integrated Circuit