HW6 - ECE 3550 DIGITAL DESIGN FALL 2006 Homework Assignment...

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ECE 3550 DIGITAL DESIGN FALL 2006 Homework Assignment #6 Total: 90 pts. Due 11:30am, Friday, October 27, 2006 A synchronous sequential circuit is given by its state transition graph on Page 2. Use the Mentor Graphics HDL Designer, ModelSim, and LeonardoSpectrum Synthesis tools along with the Xilinx Project Navigator to design, functionally simulate and compile your circuit on a Xilinx XC2C256-TQ144 chip. However, generating a bit string to actually program your design into a chip is NOT required. A Tutorial for using the MG tools along with the Xilinx Project Navigator is posted on the Class Web Page. Tasks: a) Create a project in HDL Designer using VHDL as your language. Check the syntax and compile your design from HDL Designer by launching ModelSim. You can proceed with the simulation task from here, too. Give a hard copy of your .vhd file that was compiled without any errors . (30 pts.) b) Develop a simulation script file ( .do file ) to verify the correct operation of your circuit using ModelSim. Turn in a hard copy of your .do file along with a print out
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This homework help was uploaded on 04/07/2008 for the course ECE 3550 taught by Professor Grantner during the Fall '06 term at Western Michigan.

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