Lab 1 EEE 120 (1).doc - CSE/EEE 120 Lab 1 Answer Sheet...

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CSE/EEE 120 Lab 1 Answer Sheet Half Adder, Full Adder, 4-bit Incrementer and Adder Name: FENIL PATEL Instructor/Time: Michael Goryll/ 5:30 Group Members: Aditya Sharma Date: 1/28/19, 2/4/19, Task 1-1: Build and Test the 1-Bit Half-Adder Include a picture of your Quartus circuit here: Please comment on the single biggest issue you were facing when designing the circuit. - We were supposed to remove the extra dots forming on lines. 1
Include a picture of your Quartus simulation (timing diagram) here: Did the circuit behave as expected? If no, what was wrong? Yes Please comment on the single biggest issue you were facing when simulating the circuit. We were using integer in names which was against convention 2
Task 1-2: Build and Test a 4-Bit Increment Circuit Include a picture of your Quartus circuit here: Please comment on the single biggest issue you were facing when designing the circuit. - We were supposed to remove extra dots forming on line.

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